Datasheet > BUK9K30-80E

BUK9K30-80E

更新时间： 2024-10-02 11:13:07

品牌	Logo	应用领域
安世 - NEXPERIA		/
页数	文件大小	规格书
12页	268K
描述
Dual N-channel 80 V, 30 mΩ logic level MOSFETProduction

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BUK9K30-80E 数据手册

BUK9K30-80E

Dual N-channel 80 V, 30 mΩ logic level MOSFET

12 May 2018

Product data sheet

1. General description

Dual Logic level N-channel MOSFET in an LFPAK56D (Dual Power-SO8) package using

TrenchMOS technology. This product has been designed and qualified to AEC-Q101 standard for

use in high performance automotive applications.

2. Features and benefits

•

Dual MOSFET

•

AEC-Q101 compliant

Repetitive avalanche rated

Suitable for thermally demanding environments due to 175 °C rating

True logic level gate with V_GS(th)rating of greater than 0.5 V at 175 °C

3. Applications

•

12 V, 24 V and 48 V automotive systems

Motors, lamps and solenoid control

Transmission control

Ultra high performance power switching

4. Quick reference data

Table 1. Quick reference data

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Limiting values FET1 and FET2

V_DS

I_D

drain-source voltage

drain current

25 °C ≤ T_j≤ 175 °C

V_GS= 5 V; T_mb= 25 °C; Fig. 2

P_tot

total power dissipation T_mb= 25 °C; Fig. 1

Static characteristics FET1 and FET2

R_DSon

drain-source on-state

resistance

V_GS= 5 V; I_D= 5 A; T_j= 25 °C; Fig. 11

mΩ

Dynamic characteristics FET1 and FET2

Q_GDgate-drain charge

I_D= 5 A; V_DS= 64 V; V_GS= 5 V;

T_j= 25 °C; Fig. 13; Fig. 14

6.2

30.8

Source-drain diode FET1 and FET2

Q_rrecovered charge

I_S= 5 A; dI_S/dt = -100 A/µs; V_GS= 0 V;

V_DS= 25 V; T_j= 25 °C

12 3 4 5 6 7...12

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