BU-6174X/6184X/6186X
ENHANCED MINIATURE ADVANCED
COMMUNICATIONS ENGINE
(ENHANCED MINI-ACE)
FEATURES
DESCRIPTION
FULLY INTEGRATED 1553A/B NOTICE 2,
MCAIR, STANAG 3838 INTERFACE TERMINAL
•
The Enhanced Mini-ACE family of a set of 20 instructions.This provides
MIL-STD-1553 terminals provide an autonomous means of imple-
complete interfaces between a host menting
processor and a 1553 bus. These scheduling, message retry schemes,
terminals integrate dual transceiver, data double buffering, asynchronous
protocol logic, and 4K words or 64K message insertion, and reporting to
COMPATIBLE WITH MINI-ACE (PLUS)
AND ACE GENERATIONS
•
•
multi-frame
message
CHOICE OF :
RT OR BC/RT/MT IN SAME FOOTPRINT
RT OR BC/RT/MT WITH 4K RAM
BC/RT/MT WITH 64K RAM, WITH RAM PARITY
•
•
words of RAM.
the host CPU. The Enhanced
Mini-ACE incorporates fully
•
a
CHOICE OF 5V OR 3.3V LOGIC
•
•
With a 1.0 inch square package, the autonomous built-in self-test, which
Enhanced Mini-ACE is nearly 100% provides comprehensive testing of
footprint and software compatibile the internal protocol logic and/or
with the previous generation Mini- RAM.
ACE (Plus) terminals, and is soft-
ware compatibile with the older ACE The Enhanced Mini-ACE RT offers
5V TRANSCEIVER WITH 1760 AND
MCAIR COMPATIBLE OPTIONS
COMPREHENSIVE BUILT-IN SELF-TEST
•
•
FLEXIBLE PROCESSOR/MEMORY
INTERFACE, WITH REDUCED HOST WAIT TIME
series.
the same choices of subaddress
buffering as the ACE and Mini-ACE
CHOICE OF 10, 12, 16, OR 20 MHZ CLOCK
•
•
The Enhanced Mini-ACE is powered (Plus), along with a global circular
by a choice 5V, or 5V/3.3V (3.3V buffering option, 50% rollover inter-
logic). Multiprotocol support of rupt for circular buffers, an interrupt
MIL-STD-1553A/B and STANAG status queue, and an "Auto-boot"
3838, including versions incorporat- option to support MIL-STD-1760.
ing McAir compatible transmitters, is
provided. There is a choice of 10, 12, The Enhanced Mini-ACE terminals
16, or 20 Mhz clocks. The BC/RT/MT provide the same flexibility in host
versions with 64K words of RAM interface configurations as the
HIGHLY AUTONOMOUS BC WITH
BUILT-IN MESSAGE SEQUENCE CONTROL:
FRAME SCHEDULING
•
BRANCHING
•
ASYNCHRONOUS MESSAGE INSERTION
GENEERAL PURPOSE QUEUE
USER-DEFINED INTERRUPTS
•
•
•
ADVANCED RT FUNCTIONS
•
GLOBAL CIRCULAR BUFFERING
INTERRUPT STATUS QUEUE
50% CIRCULAR BUFFER ROLLOVER
•
•
include built-in RAM parity checking.
ACE/Mini-ACE, along with a reduc-
tion in the host processor's worst
•
BC features include a built-in mes- case holdoff time.
sage sequence control engine, with
INTERRPTS
TX/RX_A
SHARED
RAM
*
TRANSCEIVER
A
CH. A
DATA
BUFFERS
PROCESSOR
D15-D0
DATA BUS
DATA BUS
TX/RX_A
TX/RX_B
DUAL
ENCODER/DECODER,
MULTIPROTOCOL
AND
MEMORY
MANAGEMENT
ADDRESS
BUFFERS
PROCESSOR
ADDRESS BUS
ADDRESS BUS
A15-A0
TRANSCEIVER
B
CH. B
TX/RX_B
TRANSPARENT/BUFFERED, STRBD, SELECT,
RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN,
MSB/LSB/DTGRT
PROCESSOR
AND
MEMORY
INTERFACE
LOGIC
PROCESSOR
AND
MEMORY
CONTROL
RT ADDRESS
RTAD4-RTAD0, RTADP
INCMD
IOEN, READYD
ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR,
8/16-BIT/DTREQ, POLARITY_SEL/DTACK
INT
INTERRUPT
REQUEST
CLK_IN, TAG_CLK,
MSTCLR,SSFLAG/EXT_TRG
MISCELLANEOUS
* SEE ORDERING INFORMATION FOR AVAILABLE MEMORY
FIGURE 1. ENHANCED MINI-ACE BLOCK DIAGRAM
2000 Data Device Corporation
©
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