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BS616LV8017EC55 PDF预览

BS616LV8017EC55

更新时间: 2024-11-13 05:16:15
品牌 Logo 应用领域
BSI 静态存储器
页数 文件大小 规格书
11页 208K
描述
Very Low Power CMOS SRAM 512K X 16 bit

BS616LV8017EC55 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
包装说明:TSOP, TSOP44,.46,32Reach Compliance Code:unknown
风险等级:5.92最长访问时间:55 ns
I/O 类型:COMMONJESD-30 代码:R-PDSO-G44
JESD-609代码:e0内存密度:8388608 bit
内存集成电路类型:STANDARD SRAM内存宽度:16
湿度敏感等级:3端子数量:44
字数:524288 words字数代码:512000
工作模式:ASYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:512KX16
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:TSOP封装等效代码:TSOP44,.46,32
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, THIN PROFILE
并行/串行:PARALLEL电源:3/5 V
认证状态:Not Qualified最大待机电流:0.0000025 A
最小待机电流:1.5 V子类别:SRAMs
最大压摆率:0.076 mA表面贴装:YES
技术:CMOS温度等级:COMMERCIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
Base Number Matches:1

BS616LV8017EC55 数据手册

 浏览型号BS616LV8017EC55的Datasheet PDF文件第2页浏览型号BS616LV8017EC55的Datasheet PDF文件第3页浏览型号BS616LV8017EC55的Datasheet PDF文件第4页浏览型号BS616LV8017EC55的Datasheet PDF文件第5页浏览型号BS616LV8017EC55的Datasheet PDF文件第6页浏览型号BS616LV8017EC55的Datasheet PDF文件第7页 
Very Low Power CMOS SRAM  
512K X 16 bit  
BS616LV8017  
Pb-Free and Green package materials are compliant to RoHS  
n FEATURES  
ŸWide VCC operation voltage : 2.4V ~ 5.5V  
n DESCRIPTION  
The BS616LV8017 is a high performance, very low power CMOS  
Static Random Access Memory organized as 524,288 by 16 bits and  
operates form a wide range of 2.4V to 5.5V supply voltage.  
Advanced CMOS technology and circuit techniques provide both  
high speed and low power features with typical CMOS standby  
current of 0.8uA at 3.0V/25OC and maximum access time of 55ns at  
3.0V/85OC.  
ŸVery low power consumption :  
VCC = 3.0V  
VCC = 5.0V  
Operation current : 31mA (Max.) at 55ns  
2mA (Max.) at 1MHz  
Standby current : 0.8uA (Typ.) at 25OC  
Operation current : 76mA (Max.) at 55ns  
10mA (Max.) at 1MHz  
Standby current : 3.5uA (Typ.) at 25OC  
ŸHigh speed access time :  
Easy memory expansion is provided by an active LOW chip enable  
(CE) and active LOW output enable (OE) and three-state output  
drivers.  
-55  
-70  
55ns(Max.) at VCC=3.0~5.5V  
70ns(Max.) at VCC=2.7~5.5V  
ŸAutomatic power down when chip is deselected  
ŸEasy expansion with CE and OE options  
ŸI/O Configuration x8/x16 selectable by LB and UB pin.  
ŸThree state outputs and TTL compatible  
ŸFully static operation  
The BS616LV8017 has an automatic power down feature, reducing  
the power consumption significantly when chip is deselected.  
The BS616LV8017 is available in DICE form, JEDEC standard  
44-pin TSOP II and 48-ball BGA package.  
ŸData retention supply voltage as low as 1.5V  
n POWER CONSUMPTION  
POWER DISSIPATION  
Operating  
STANDBY  
PRODUCT  
FAMILY  
OPERATING  
TEMPERATURE  
PKG TYPE  
(ICCSB1, Max)  
(ICC, Max)  
VCC=5.0V  
10MHz  
VCC=3.0V  
10MHz  
VCC=5.0V VCC=3.0V  
1MHz  
9mA  
fMax.  
1MHz  
fMax.  
BS616LV8017DC  
BS616LV8017EC  
BS616LV8017FI  
BS616LV8017EI  
BS616LV8017FI  
DICE  
Commercial  
25uA  
50uA  
4.0uA  
8.0uA  
39mA  
40mA  
75mA  
1.5mA  
19mA  
20mA  
30mA  
TSOP II-44  
BGA-48-0912  
TSOP II-44  
BGA-48-0912  
+0OC to +70OC  
Industrial  
10mA  
76mA  
2mA  
31mA  
-40OC to +85OC  
n PIN CONFIGURATIONS  
n BLOCK DIAGRAM  
A4  
A3  
A2  
A1  
A0  
1
2
3
4
5
6
7
8
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
A5  
A6  
A7  
OE  
UB  
LB  
DQ15  
DQ14  
DQ13  
DQ12  
VSS  
VCC  
DQ11  
DQ10  
DQ9  
DQ8  
A8  
A13  
A12  
A11  
CE  
DQ0  
DQ1  
DQ2  
DQ3  
VCC  
VSS  
DQ4  
DQ5  
DQ6  
DQ7  
WE  
A18  
A17  
A16  
A15  
A14  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
Address  
Input  
1024  
Memory Array  
10  
9
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
Row  
Decoder  
BS616LV8017EC  
BS616LV8017EI  
Buffer  
1024 x 8192  
8192  
A9  
A10  
A11  
A12  
A13  
DQ0  
Data  
Input  
Buffer  
16  
16  
Column I/O  
.
.
.
.
.
.
.
.
Write Driver  
Sense Amp  
.
16  
.
16  
Data  
Output  
Buffer  
1
2
3
4
5
6
512  
.
.
A
B
C
D
E
F
LB  
OE  
A0  
A1  
A2  
NC  
Column Decoder  
DQ15  
D8  
D9  
UB  
D10  
D11  
D12  
D13  
NC  
A3  
A5  
A4  
A6  
CE  
D1  
D0  
D2  
9
CE  
WE  
OE  
UB  
LB  
Address Input Buffer  
Control  
VSS  
VCC  
D14  
D15  
A18  
A17  
NC  
A14  
A12  
A9  
A7  
D3  
VCC  
VSS  
D6  
A14 A15 A16 A17 A18 A0 A1 A2 A3  
VCC  
VSS  
A16  
A15  
A13  
A10  
D4  
D5  
G
H
WE  
A11  
D7  
A8  
NC  
48-ball BGA top view  
Brilliance Semiconductor, Inc. reserves the right to change products and specifications without notice.  
R0201-BS616LV8017  
Revision 2.3  
May. 2006  
1

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