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BS616LV8017EIG70 PDF预览

BS616LV8017EIG70

更新时间: 2024-11-12 22:37:15
品牌 Logo 应用领域
BSI 静态存储器
页数 文件大小 规格书
9页 273K
描述
Very Low Power/Voltage CMOS SRAM 512K X 16 bit

BS616LV8017EIG70 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSOP2包装说明:TSOP2, TSOP44,.46,32
针数:44Reach Compliance Code:unknown
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.82最长访问时间:70 ns
I/O 类型:COMMONJESD-30 代码:R-PDSO-G44
长度:18.41 mm内存密度:8388608 bit
内存集成电路类型:STANDARD SRAM内存宽度:16
湿度敏感等级:3功能数量:1
端子数量:44字数:524288 words
字数代码:512000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:512KX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TSOP2
封装等效代码:TSOP44,.46,32封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE并行/串行:PARALLEL
电源:3/5 V认证状态:Not Qualified
座面最大高度:1.2 mm最大待机电流:0.0000025 A
最小待机电流:1.5 V子类别:SRAMs
最大压摆率:0.061 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):2.4 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:GULL WING
端子节距:0.8 mm端子位置:DUAL
宽度:10.16 mm

BS616LV8017EIG70 数据手册

 浏览型号BS616LV8017EIG70的Datasheet PDF文件第2页浏览型号BS616LV8017EIG70的Datasheet PDF文件第3页浏览型号BS616LV8017EIG70的Datasheet PDF文件第4页浏览型号BS616LV8017EIG70的Datasheet PDF文件第5页浏览型号BS616LV8017EIG70的Datasheet PDF文件第6页浏览型号BS616LV8017EIG70的Datasheet PDF文件第7页 
Very Low Power/Voltage CMOS SRAM  
512K X 16 bit  
(Single CE Pin)  
BSI  
BS616LV8017  
„ FEATURES  
• Fully static operation  
• Data retention supply voltage as low as 1.5V  
• Easy expansion with CE and OE options  
• Wide Vcc operation voltage : 2.4~5.5V  
• Very low power consumption :  
Vcc = 3.0V C-grade: 30mA (@55ns) operating current  
I -grade: 31mA (@55ns) operating current  
C-grade: 24mA (@70ns) operating current  
I -grade: 25mA (@70ns) operating current  
1.5uA (Typ.) CMOS standby current  
Vcc = 5.0V C-grade: 75mA (@55ns) operating current  
I -grade: 76mA (@55ns) operating current  
C-grade: 60mA (@70ns) operating current  
I -grade: 61mA (@70ns) operating current  
8.0uA (Typ.) CMOS standby current  
• I/O Configuration x8/x16 selectable by LB and UB pin  
„ DESCRIPTION  
The BS616LV8017 is a high performance, very low power CMOS Static  
Random Access Memory organized as 524,288 words by 16 bits and  
operates from a wide range of 2.4V to 5.5V supply voltage.  
Advanced CMOS technology and circuit techniques provide both high  
speed and low power features with a typical CMOS standby current  
of 1.5uA at 3V/25oC and maximum access time of 55ns at 3.0V/85oC.  
Easy memory expansion is provided by an active LOW chip enable (CE)  
,active LOW output enable(OE) and three-state output drivers.  
• High speed access time :  
-55  
-70  
55ns  
70ns  
The BS616LV8017 has an automatic power down feature, reducing the  
power consumption significantly when chip is deselected.  
The BS616LV8017 is available in 48B BGA and 44L TSOP2 packages.  
• Automatic power down when chip is deselected  
• Three state outputs and TTL compatible  
„ PRODUCT FAMILY  
POWER DISSIPATION  
SPEED  
( ns )  
STANDBY  
Operating  
PRODUCT  
FAMILY  
OPERATING  
TEMPERATURE  
Vcc  
RANGE  
( ICCSB1, Max )  
( ICC, Max )  
PKG TYPE  
Vcc=5V  
70ns  
Vcc=3V  
70ns  
55ns : 3.0~5.5V  
70ns : 2.7~5.5V  
Vcc=3V  
Vcc=5V  
BS616LV8017EC  
BS616LV8017FC  
BS616LV8017EI  
BS616LV8017FI  
TSOP2-44  
BGA-48-0912  
TSOP2-44  
+0O C to +70OC 2.4V ~ 5.5V  
-40OC to +85OC 2.4V ~ 5.5V  
55 / 70  
55 / 70  
5uA  
55uA  
24mA  
25mA  
60mA  
10uA  
110uA  
61mA  
BGA-48-0912  
„ PIN CONFIGURATIONS  
„ BLOCK DIAGRAM  
1
2
3
4
5
6
7
8
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
24  
23  
A4  
A3  
A2  
A1  
A0  
CE  
DQ0  
DQ1  
A5  
A6  
A7  
OE  
UB  
LB  
DQ15  
DQ14  
DQ13  
DQ12  
Vss  
A4  
A3  
A2  
A1  
A0  
Address  
Input  
22  
2048  
9
DQ2  
DQ3  
Vcc  
A17  
A16  
Row  
Memory Array  
2048 x 4096  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
BS616LV8017EC  
BS616LV8017EI  
Buffer  
Vss  
Vcc  
A15  
A14  
A13  
A12  
Decoder  
DQ4  
DQ5  
DQ6  
DQ7  
WE  
A18  
A17  
A16  
A15  
A14  
DQ11  
DQ10  
DQ9  
DQ8  
A8  
4096  
A9  
A10  
A11  
A12  
A13  
Data  
Input  
16  
16  
Column I/O  
D0  
Buffer  
.
.
.
.
.
.
.
.
Write Driver  
Sense Amp  
1
2
3
4
6
16  
5
A2  
256  
Data  
Output  
16  
LB  
OE  
A0  
A1  
NC  
A
B
C
D
E
F
Buffer  
Column Decoder  
D15  
D8  
D9  
UB  
A3  
A5  
A4  
A6  
A7  
CE  
D1  
D3  
D0  
D2  
D10  
D11  
16  
CE  
V
A17  
V
CC  
SS  
SS  
CC  
WE  
OE  
UB  
Control  
Address Input Buffer  
A16  
A 15  
A13  
A10  
D4  
D5  
VSS  
A14  
A12  
A9  
V
V
D12  
D13  
D6  
D14  
D15  
A18  
LB  
A11 A10 A9 A8 A7  
A6 A5 A18  
WE  
A11  
D7  
N.C  
A8  
Vcc  
Vss  
G
H
NC  
48-Ball CSP top View  
Brilliance Semiconductor, Inc. reserves the right to modify document contents without notice.  
Revision 2.1  
R0201-BS616LV8017  
1
Jan.  
2004  

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