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BGU8821A

更新时间: 2022-06-24 15:43:02
品牌 Logo 应用领域
恩智浦 - NXP 光电二极管
页数 文件大小 规格书
41页 566K
描述
Dual channel low-noise high linearity amplifier with DSA and SPDT

BGU8821A 数据手册

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NXP Semiconductors  
BGU8821/A  
Dual channel low-noise high linearity amplifier with DSA and SPDT  
8.1.2 Direct DSA Attenuation mode  
In Direct DSA Attenuation mode, Main and Diversity DSAs can be toggled independently  
without accessing SPI bus.  
Pin 9 <DSA_0_X_dB Main> can be toggled to set DSA_M between Minimum Attenuation  
(level LOW) and predefined X dB attenuation (level HIGH). X dB attenuation is defined in  
DSA_M_TDD_ATTN (register 0x16h, bits [6-2]). Default reset value is 15 dB.  
Table 6.ꢀDirect DSA Attenuation mode for Main channel truth table  
Legend: * reset value  
Pin 9  
DIRECT_DSA_M  
DSA_M Attenuation  
Description  
DSA_0_X dB Main  
register 0x13h, bit [1]  
0
1
0*  
0*  
Min attenuation IL  
IL x X dB Attenuation  
X dB is set in register 0x16h,  
default value is 15 dB  
x
1
SPI setting  
DSA_M controlled by SPI  
using register 0x11h, default  
value is Min attenuation, IL  
Pin 23 <GPO/DSA_0_X_dB Diversity> can be toggled to set DSA_M between Minimum  
Attenuation (level LOW) and predefined X dB attenuation (level HIGH). X dB attenuation  
is defined in DSA_D_TDD_ATTN (register 0x17h, bits [6-2]). Default reset value is 15 dB.  
Table 7.ꢀDirect DSA Attenuation mode for Diversity channel truth table  
Legend: * reset value  
Pin 23  
DIRECT_DSA_D  
DSA_D Attenuation  
Description  
DSA_0_X dB Diversity  
register 0x13h, bit [2]  
0
1
0*  
0*  
Min attenuation IL  
IL x X dB Attenuation  
X dB is set in register 0x17h,  
default value is 15 dB  
GPO functionality  
1
SPI setting  
DSA_D controlled by SPI  
using register 0x12h, default  
value is Min attenuation, IL  
By default, the BGU8821/A starts up in Direct DSA Attenuation mode. This mode can be  
switched off via register 0x13h, bits [1] (for the Main channel) and [2] (for the Diversity  
channel). While Direct DSA Attenuation mode for Diversity channel is active, GPO  
functionality is not available.  
When DIRECT_DSA_D (register 0x13h bit [2]) is set HIGH, Direct DSA Attenuation mode  
for Diversity channel is switched off and Pin 23 is used as <GPO> pin.  
8.2 Serial Peripheral interface (SPI) Bus  
The Serial Peripheral Interface (SPI) bus allows simple interfacing with many industry  
microprocessors; it provides access to all the registers that define the operation of the  
BGU8821/A.  
BGU8821/A  
All information provided in this document is subject to legal disclaimers.  
© NXP B.V. 2020. All rights reserved.  
Product data sheet  
Rev. 6 — 15 April 2020  
7 / 41  
 
 

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