Datasheet > BGU8821A

BGU8821A

更新时间： 2024-01-27 09:56:04

品牌	Logo	应用领域
恩智浦 - NXP		光电二极管
页数	文件大小	规格书
41页	566K
描述
Dual channel low-noise high linearity amplifier with DSA and SPDT

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BGU8821A 数据手册

NXP Semiconductors

BGU8821/A

Dual channel low-noise high linearity amplifier with DSA and SPDT

7 Pinning information

7.1 Pinning

terminal 1

index area

GND

VDD_SPI

RFIN_M

33 VDD_SPDT

32 GND/Disable Main channel

31 SW_RF2

GND

SCLK

CSB

30 GND

29 GND

exposed die pad

SDIO

28 SW_RFC

SDO

27 GND

DSA_0_X dB Main

26 GND

GND 10

25 SW_RF1

RFIN_D 11

24 GND/Disable Diversity channel

GND 12

GPO/DSA_0_X dB Diversity

aaa-020600

Transparent top view

Multiple power and ground pins allows for independent supply domains to improve cross channel isolation and between

blocks in one single channel. In, order to reduce series inductance at all RF ports and RF grounding a small package

footprint was chosen.

Figure 2.ꢀPin configuration

7.2 Pin description

Table 5.ꢀPin description

Symbol

Description

GND

1, 3, 4, 10, 12,

14,16, 17, 19, 20,

26, 27, 29, 30, 37,

38,40, 41,43

Ground

RFIN_M

RF Input to LNA1, main channel. An external DC block is required. External

SMD is required for matching.

SCLK

Clock input for SPI

CSB

Chip select active low

SDIO

Serial data in/out. Push-Pull pin

Serial data out. Push-Pull pin

SDO

DSA_0_X dB Main

Direct-access DSA setting between minimum attenuation and X dB

attenuation programmed prior to TDD mode, main channel

BGU8821/A

All information provided in this document is subject to legal disclaimers.

Product data sheet

Rev. 6 — 15 April 2020

4 / 41

1 2 345 6 7...41

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