ARIZONA MICROTEK, INC.
AZ10EL31
AZ100EL31
ECL/PECL D Flip-Flop with Set and Reset
PACKAGE AVAILABILITY
FEATURES
PACKAGE
SOIC 8
PART NO.
AZ10EL31D
MARKING
AZM10EL31
AZM10EL31
AZM10EL31
AZM100EL31
•
•
•
•
475ps Propagation Delay
2.8GHz Toggle Frequency
SOIC 8 T&R
SOIC 8 T&R
SOIC 8
AZ10EL31DR1
AZ10EL31DR2
AZ100EL31D
75kΩ Internal Input Pulldown Resistors
Direct Replacement for ON Semiconductor
MC10EL31 & MC100EL31
SOIC 8 T&R
SOIC 8 T&R
TSSOP 8
TSSOP 8 T&R AZ10EL31TR1
TSSOP 8 T&R AZ10EL31TR2
AZ100EL31DR1 AZM100EL31
AZ100EL31DR2 AZM100EL31
AZ10EL31T
AZTEL31
AZTEL31
AZTEL31
AZHEL31
TSSOP 8
AZ100EL31T
TSSOP 8 T&R AZ100EL31TR1 AZHEL31
TSSOP 8 T&R AZ100EL31TR2 AZHEL31
DESCRIPTION
The AZ10/100EL31 is a master-slave D flip-flop with set and reset. The device is functionally equivalent to the
E131 device with higher performance capabilities. With propagation delays and output transition times significantly
faster than the E131, the EL31 is ideally suited for those applications that require the ultimate in AC performance.
Both set and reset inputs are asynchronous, level triggered signals. Data enters the master section of the flip-
flop when the clock is LOW. When the clock transitions from LOW to HIGH, the data in the master section
transfers into the slave section and through to the outputs.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.
TRUTH TABLE
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
D
S*
R*
CLK
Q
Q¯
L
H
X
X
X
L
L
H
L
H
L
L
L
H
H
Z
Z
L
H
H
L
H
L
L
H
1
2
3
4
8
V
S
D
CC
X
X
X
S
Undef Undef
D
Q
7
6
5
Z = LOW to HIGH Transition
Flip Flop
R
* Pins will default low when left open
PIN DESCRIPTION
Q
CLK
R
PIN
FUNCTION
S
Set Input
V
D
R
Data Input
EE
Reset Input
CLK
Q, Q¯
VCC
Clock Input
Data Outputs
Positive Supply
Negative Supply
VEE
1630 S. STAPLEY DR., SUITE 125 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541
www.azmicrotek.com