ARIZONA MICROTEK, INC.
AZ10EL32
AZ100EL32
ECL/PECL ÷ 2 Divider
PACKAGE AVAILABILITY
FEATURES
PACKAGE
PART NUMBER
MARKING NOTES
•
•
•
•
•
510ps Propagation Delay
AZM10
EL32
SOIC 8
AZ10EL32D
1,2
3.0GHz Toggle Frequency
High Bandwidth Output Transitions
75kΩ Internal Input Pulldown Resistors
Direct Replacement for ON
Semiconductor MC10EL32 &
MC100EL32
AZM100
EL32
SOIC 8
AZ100EL32D
AZ100EL32D+
1,2
SOIC 8 RoHS
Compliant / Lead
(Pb) Free
AZM100+
1,2
EL32
AZT
1,2
TSSOP 8
TSSOP 8
AZ10EL32T
EL32
AZH
EL32
AZ100LVEL32T
1,2
1
2
Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K parts)
Tape & Reel.
Date code format: “Y” or “YY” for year followed by “WW” for week on
underside of part.
DESCRIPTION
The AZ10/100EL32 is an integrated ÷2 divider. The reset pin is asynchronous and is asserted on the rising edge.
Upon power-up, the internal flip-flop will attain a random logic state; the reset allows for the synchronization of
multiple EL32’s in a system.
The EL32 provides a VBB output for single-ended use or a DC bias reference for AC coupling to the device. For
single-ended input applications, the VBB reference should be connected to one side of the CLK/¯C¯L¯K¯ differential input
pair. The input signal is then fed to the other CLK/C¯¯L¯K¯ input. The VBB pin should be used only as a bias for the
EL32 as its sink/source capability is limited. When used, the VBB pin should be bypassed to ground via a 0.01μF
capacitor.
NOTE: Specifications in ECL/PECL tables are valid when thermal equilibrium is established.
LOGIC DIAGRAM AND PINOUT ASSIGNMENT
VCC
1
8
RESET
CLK
PIN DESCRIPTION
FUNCTION
R
PIN
2
3
4
7
6
5
Q
Q
CLK, C¯L¯¯K Clock Inputs
RESET
VBB
Q, Q¯
VCC
Asynchronous Reset
Reference Voltage Output
Data Outputs
÷2
CLK
VBB
Positive Supply
VEE
Negative Supply
VEE
1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541
www.azmicrotek.com