Datasheet > AZ10ELT20

AZ10ELT20

更新时间： 2024-09-21 04:33:23

品牌	Logo	应用领域
AZM		转换器
页数	文件大小	规格书
10页	114K
描述
CMOS/TTL to Differential PECL Translator

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数据手册

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AZ10ELT20 数据手册

ARIZONA MICROTEK, INC.

AZ10ELT20

AZ100ELT20

CMOS/TTL to Differential PECL Translator

PACKAGE AVAILABILITY

FEATURES

PACKAGE

PART NUMBER

MARKING NOTES

•

0.5ns Typical Propagation Delay

Differential PECL Outputs

Flow Through Pinouts

Operating Range of +3.0V to +5.5V

Direct Replacement for ON Semi

MC100ELT20 & Micrel SY89329V

Available in 2x2 and 3x3 mm MLP

Packages

MLP 8 (2x2x0.75)

AZ100ELT20N

1,2

MLP 8 (2x2x0.75)

Green / RoHS

Compliant / Lead

(Pb) Free

TCG

AZ100ELT20NG

AZ10/100ELT20L

AZ10/100ELT20LG

1,2

AZM

•

MLP 16 (3x3)

T20

1,2

IBIS Model Files Available on

Arizona Microtek Website

MLP 16 (3x3)

Green / RoHS

Compliant / Lead

(Pb) Free

AZMG

T20

AZM10

ELT20

AZM100

ELT20

SOIC 8

AZ10ELT20D

AZ100ELT20D

1,2,3

SOIC 8 RoHS

Compliant / Lead

(Pb) Free

AZM100+

ELT20

AZ100ELT20D+

1,2,3

SOIC 8 Green /

RoHS Compliant /

Lead (Pb) Free

DESCRIPTION

AZM100G

ELT20

AZ100ELT20DG

AZ100ELT20T

1,2,3

AZH

LT20

The

AZ10/100ELT20

TSSOP 8

CMOS/TTL to differential PECL

translator. It operates with a single power

supply of +3.0 to +5.5 volts, making it

ideal for both LVCMOS/LVTTL and

CMOS/TTL applications. The extremely

small MLP 8 2x2 mm package makes it

ideal for those applications where space,

performance and low power are at a

premium.

TSSOP 8 Green /

RoHS Compliant /

Lead (Pb) Free

DIE

AZHG

LT20

AZ100ELT20TG

1,2,3

AZ10/100ELT20XP

N/A

Add R1 at end of part number for 7 inch (1K parts), R2 for 13 inch (2.5K

parts) Tape & Reel.

Date code format: “Y” or “YY” for year followed by “WW” for week.

Date code “YWW” or “YYWW” on underside of part.

Waffle Pack.

When the D input is left floating, the Q output is forced HIGH, and the Q¯ output is forced LOW.

The ELT20 is available in both PECL standards: the AZ10ELT20 is compatible with PECL 10K logic levels

while the AZ100ELT20 is compatible with PECL 100K logic levels.

NOTE: Specifications in the PECL tables are valid when thermal equilibrium is established.

BLOCK DIAGRAM

1630 S. STAPLEY DR., SUITE 127 • MESA, ARIZONA 85204 • USA • (480) 962-5881 • FAX (480) 890-2541

www.azmicrotek.com

12 3 4 5 6 7...10

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