VCE6467T, AVCE6467T
SPRS690–MARCH 2011
www.ti.com
(BT.1120), or Single Raw (8-/10-/12-Bit) Video
Capture Channels
• 32-Bit, 66-MHz, 3.3 V Peripheral Component
Interconnect (PCI) Master/Slave Interface
– Two 8-Bit SD (BT.656) or Single 16-Bit HD
(BT.1120) Video Display Channels
• Video Data Conversion Engine (VDCE)
– Horizontal and Vertical Downscaling
– Chroma Conversion (4:2:2↔4:2:0)
– Conforms to PCI Specification 2.3
• Two 64-Bit General-Purpose Timers (Each
Configurable as Two 32-Bit Timers)
• One 64-Bit Watch Dog Timer
• Three Configurable UART/IrDA/CIR Modules
(One With Modem Control Signals)
• Two Transport Stream Interface (TSIF) Modules
(One Parallel/Serial and One Serial Only)
– Supports up to 1.8432 Mbps UART
– SIR and MIR (0.576 MBAUD)
– TSIF for MPEG Transport Stream
– Simultaneous Synchronous or
– CIR With Programmable Data Encoding
Asynchronous Input/Output Streams
– Absolute Time Stamp Detection
– PID Filter With 7 PID Filter Tables
– Corresponding Clock Reference Generator
(CRGEN) Modules for System Time-Clock
Recovery
• One Serial Peripheral Interface (SPI) With Two
Chip-Selects
• Master/Slave Inter-Integrated Circuit (I2C Bus™)
• Two Multichannel Audio Serial Ports (McASPs)
– One Four Serializer Transmit/Receive Port
– One Single DIT Transmit Port for S/PDIF
• 32-Bit Host Port Interface (HPI)
• External Memory Interfaces (EMIFs)
– Up to 400-MHz 32-Bit DDR2 SDRAM Memory
Controller With 512M-Byte Address Space
(1.8-V I/O)
– Asynchronous16-Bit Wide EMIF (EMIFA)
With 128M-Byte Address Reach
• VLYNQ™ Interface (FPGA Interface)
• Two Pulse Width Modulator (PWM) Outputs
• ATA/ATAPI I/F (ATA/ATAPI-6 Specification)
• Up to 33 General-Purpose I/O (GPIO) Pins
(Multiplexed With Other Device Functions)
• On-Chip ARM ROM Bootloader (RBL)
• Individual Power-Saving Modes for ARM/DSP
• Flexible PLL Clock Generators
• IEEE-1149.1 (JTAG) Boundary-
Scan-Compatible
• 529-Pin Pb-Free BGA Package
(ZUT Suffix), 0.8-mm Ball Pitch
• 0.09-μm/7-Level Cu Metal Process (CMOS)
• 3.3-V and 1.8-V I/O, 1.3-V Internal
• Applications:
•
Flash Memory Interfaces
–
–
NOR (8-/16-Bit-Wide Data)
NAND (8-/16-Bit-Wide Data)
• Enhanced Direct-Memory-Access (EDMA)
Controller (64 Independent Channels)
– Programmable Default Burst Size
• 10/100/1000 Mb/s Ethernet MAC (EMAC)
– IEEE 802.3 Compliant (3.3-V I/O Only)
– Supports MII and GMII Media Independent
Interfaces
– Management Data I/O (MDIO) Module
• USB Port With Integrated 2.0 PHY
– USB 2.0 High-/Full-Speed Client
– Video Encode/Decode/Transcode/Transrate
– Digital Media
– Networked Media Encode/Decode
– Video Imaging
– USB 2.0 High-/Full-/Low-Speed Host
(Mini-Host, Supporting One External
Device)
– Video Infrastructure
– Video Conferencing
2
Digital Media System-on-Chip (DMSoC)
Copyright © 2011, Texas Instruments Incorporated
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