5.
Speed/Power Management
The ATF1502AS(L) has several built-in speed and power management features. The ATF1502AS(L) contains
circuitry which automatically puts the device into a low-power standby mode when no logic transitions are occurring.
This not only reduces power consumption during inactive periods, but also provides proportional power savings for
most applications running at system speeds below 50MHz. This feature may be selected as a design option.
To further reduce power, each ATF1502AS(L) macrocell has a reduced-power bit feature. This feature allows
individual macrocells to be configured for maximum power savings. This feature may be selected as a design
option.
The ATF1502AS(L) also has an optional power-down mode. In this mode, current drops to below 10mA. When
the power-down option is selected, either PD1 or PD2 pins (or both) can be used to power down the part. The
power-down option is selected in the design source file. When enabled, the device goes into power-down when
either PD1 or PD2 is high. In the power-down mode, all internal logic signals are latched and held, as are any
enabled outputs.
All pin transitions are ignored until the PD pin is brought low. When the power-down feature is enabled, the PD1
or PD2 pin cannot be used as a logic input or output; however, the pin’s macrocell may still be used to generate
buried foldback and cascade logic signals.
All power-down AC characteristic parameters are computed from external input or I/O pins, with reduced-power
bit turned on. For macrocells in reduced-power mode (reduced-power bit turned on), the reduced-power adder,
t
RPA, must be added to the AC parameters, which include the data paths tLAD, tLAC, tIC, tACL, tACH, and tSEXP.
The ATF1502AS(L) macrocell also has an option whereby the power can be reduced on a per-macrocell basis.
By enabling this power-down option, macrocells that are not used in an application can be turned down, thereby
reducing the overall power consumption of the device.
Each output also has individual slew rate control. This may be used to reduce system noise by slowing down
outputs that do not need to operate at maximum speed. Outputs default to slow switching, and may be specified
as fast switching in the design file.
6.
7.
Design Software Support
ATF1502AS(L) designs are supported by several third-party tools. Automated fitters allow logic synthesis using
a variety of high-level description languages and formats.
Power-up Reset
The ATF1502AS(L) is designed with a power-up reset, a feature critical for state machine initialization. At a
point delayed slightly from VCC crossing VRST, all registers will be initialized, and the state of each output will
depend on the polarity of its buffer. However, due to the asynchronous nature of reset and uncertainty of how
VCC actually rises in the system, the following conditions are required:
The VCC rise must be monotonic,
After reset occurs, all input and feedback setup times must be met before driving the clock pin high, and,
The clock must remain stable during TD.
The ATF1502AS(L) has two options for the hysteresis about the reset level, VRST, Small and Large. During the
fitting process, users may configure the device with the Power-up Reset hysteresis set to Large or Small. Atmel
POF2JED users may select the Large option by including the flag “-power_reset” on the command line after
“filename.POF”. To allow the registers to be properly reinitialized with the Large hysteresis option selected, the
following condition is added:
If VCC falls below 2.0V, it must shut off completely before the device is turned on again.
When the Large hysteresis option is active, ICC is reduced by several hundred micro amps as well.
8
ATF1502AS(L) [DATASHEET]
Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014
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