Datasheet > ATF1502AS-7JX44-T

ATF1502AS-7JX44-T

更新时间： 2022-12-01 22:24:20

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ATF1502AS-7JX44-T 数据手册

Block Diagram

Figure 2-1.

Block Diagram

Logic Block A

Macrocells

1 to 16

Logic Block B

I/O Pins

Output

Enable

Switch

Matrix

GOE[0:5]

Global

Clock

Mux

I/O (MC32)/GCLK3

GCK[0:2]

OE1/INPUT

INPUT/GCLK1

INPUT/OE2/GCLK2

Global

Clear

Mux

GCLEAR

INPUT/GCLR

Unused product terms are automatically disabled by the compiler to decrease power consumption. A security

fuse, when programmed, protects the contents of the ATF1502AS(L). Two bytes (16 bits) of User Signature are

accessible to the user for purposes such as storing project name, part number, revision, or date. The User

Signature is accessible regardless of the state of the security fuse.

The ATF1502AS(L) device is an In-System Programmable (ISP) device. It uses the industry standard 4-pin

JTAG interface (IEEE Std. 1149.1), and is fully compliant with JTAG’s Boundary-scan Description Language

(BSDL). ISP allows the device to be programmed without removing it from the printed circuit board. In addition

to simplifying the manufacturing flow, ISP also allows design modifications to be made in the field via software.

ATF1502AS(L) [DATASHEET]

Atmel-0995L-CPLD-ATF1502AS(L)-Datasheet_032014

1 2 3 456 7 8...29

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