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ATC600F2R2BT250XT

更新时间： 2024-11-27 01:08:15
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恩智浦 - NXP 电容器
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18页 673K
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RF LDMOS Wideband Integrated Power Amplifiers

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Document Number: MD7IC18120N  
Rev. 0, 5/2010  
Freescale Semiconductor  
Technical Data  
RF LDMOS Wideband Integrated  
Power Amplifiers  
MD7IC18120NR1  
MD7IC18120GNR1  
The MD7IC18120N/GN wideband integrated circuit is designed with on--chip  
matching that makes it usable from 1805 to 1880 MHz. This multi--stage  
structure is rated for 26 to 32 Volt operation and covers all typical cellular base  
station modulation formats.  
1805--1880 MHz, 30 W AVG., 28 V  
SINGLE W--CDMA  
RF LDMOS WIDEBAND  
INTEGRATED POWER AMPLIFIERS  
•
Typical Doherty Single--Carrier W--CDMA Performance: VDD = 28 Volts,  
IDQ1A = 70 mA, IDQ1B = 160 mA, IDQ2B = 500 mA, VGS2A = 1.7 Vdc, Pout  
30 Watts Avg., IQ Magnitude Clipping, Channel Bandwidth = 3.84 MHz,  
Input Signal PAR = 7.5 dB @ 0.01% Probability on CCDF.  
=
G
PAE  
(%)  
Output PAR  
(dB)  
ps  
Frequency  
1805 MHz  
1840 MHz  
1880 MHz  
(dB)  
25.7  
25.7  
25.8  
CASE 1866--02  
TO--270 WBL--16  
PLASTIC  
36.7  
36.3  
35.3  
6.9  
6.9  
6.7  
MD7IC18120NR1  
•
Capable of Handling 10:1 VSWR, @ 32 Vdc, 1840 MHz, 140 Watts CW  
Output Power  
•
•
Stable into a 5:1 VSWR. All Spurs Below --60 dBc @ 100 Watts CW Pout  
Typical Pout @ 1 dB Compression Point ≃ 120 Watts CW  
Features  
CASE 1867--02  
TO--270 WBL--16 GULL  
PLASTIC  
•
•
•
Production Tested in a Symmetrical Doherty Configuration  
100% PAR Tested for Guaranteed Output Power Capability  
Characterized with Large--Signal Load--Pull Parameters and Common  
Source S--Parameters  
MD7IC18120GNR1  
•
•
•
•
•
•
•
On--Chip Matching (50 Ohm Input, DC Blocked)  
Integrated Quiescent Current Temperature Compensation with Enable/Disable Function (1)  
Integrated ESD Protection  
Greater Negative Gate--Source Voltage Range for Improved Class C Operation  
225°C Capable Plastic Package  
RoHS Compliant  
In Tape and Reel. R1 Suffix = 500 Units per 44 mm, 13 inch Reel.  
V
V
DS1A  
N.C.  
DS1A  
GS2A  
1
2
3
V
V
V
Quiescent Current  
Temperature Compensation  
GS2A  
GS1A  
(1)  
V
16  
15  
4
GS1A  
N.C.  
RF /V  
outA DS2A  
5
(2)  
RF  
6
PEAKING  
RF /V  
inA  
N.C.  
7
RF  
inA  
inB  
outA DS2A  
N.C.  
8
9
RF  
inB  
N.C.  
10  
11  
12  
13  
14  
RF /V  
outB DS2B  
V
GS1B  
GS2B  
DS1B  
N.C.  
V
RF  
RF /V  
outB DS2B  
V
(2)  
CARRIER  
(Top View)  
V
V
GS1B  
GS2B  
Quiescent Current  
Temperature Compensation  
(1)  
Note: Exposed backside of the package is  
the source terminal for the transistors.  
V
DS1B  
Figure 1. Functional Block Diagram  
Figure 2. Pin Connections  
1. Refer to AN1977, Quiescent Current Thermal Tracking Circuit in the RF Integrated Circuit Family and to AN1987, Quiescent Current Control  
for the RF Integrated Circuit Device Family. Go to http://www.freescale.com/rf. Select Documentation/Application Notes -- AN1977 orAN1987.  
2. Peaking and Carrier orientation is determined by the test fixture design.  
© Freescale Semiconductor, Inc., 2010. All rights reserved.  
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