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AT25128AN-10SA-5.0C PDF预览

AT25128AN-10SA-5.0C

更新时间： 2024-11-06 02:59:39
品牌 Logo 应用领域
爱特美尔 - ATMEL 可编程只读存储器电动程控只读存储器电可擦编程只读存储器光电二极管
页数 文件大小 规格书
17页 401K
描述
EEPROM, 16KX8, Serial, CMOS, PDSO8, 0.150 INCH, PLASTIC, MS-012AA, SOIC-8

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AT25128AN-10SA-5.0C 数据手册

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Features  
• Serial Peripheral Interface (SPI) Compatible  
• Supports SPI Modes 0 (0,0) and 3 (1,1)  
– Data Sheet Describes Mode 0 Operation  
• Medium-voltage and Standard-voltage Operation  
– 5.0 (VCC = 4.5V to 5.5V)  
– 2.7 (VCC = 2.7V to 5.5V)  
• 5 MHz Clock Rate  
• 64-byte Page Mode and Byte Write Operation  
• Block Write Protection  
– Protect 1/4, 1/2, or Entire Array  
SPI Serial  
• Write Protect (WP) Pin and Write Disable Instructions for  
both Hardware and Software Data Protection  
• Self-timed Write Cycle (5 ms max)  
• High Reliability  
– Endurance: 100,000 Write Cycles  
– Data Retention: >100 Years  
• 8-lead PDIP and 8-lead JEDEC SOIC Packages  
Automotive  
EEPROMs  
128K (16,384 x 8)  
256K (32,768 x 8)  
Description  
The AT25128A/256A provides 131,072/262,144 bits of serial electrically-erasable pro-  
grammable read-only memory (EEPROM) organized as 16,384/32,768 words of 8 bits  
each. The device is optimized for use in many industrial and commercial applications  
where low-power and low-voltage operation are essential. The devices are available in  
space saving 8-lead PDIP and 8-lead JEDEC SOIC packages. In addition, the entire  
family is available in 5.0V (4.5V to 5.5V) and 2.7V (2.7V to 5.5V) versions.  
AT25128A  
AT25256A  
The AT25128A/256A is enabled through the Chip Select pin (CS) and accessed via a  
three-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and  
Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa-  
rate erase cycle is required before write.  
Block write protection is enabled by programming the status register with top one-  
quarter, top one-half or entire array of write protection. Separate Program Enable and  
Program Disable instructions are provided for additional data protection. Hardware  
data protection is provided via the WP pin to protect against inadvertent write attempts  
to the status register. The HOLD pin may be used to suspend any serial communica-  
tion without resetting the serial sequence.  
Table 1. Pin Configurations  
Pin Name  
CS  
Function  
8-lead PDIP  
Chip Select  
CS  
SO  
1
2
3
4
8
7
6
5
VCC  
HOLD  
SCK  
SI  
SCK  
SI  
Serial Data Clock  
Serial Data Input  
Serial Data Output  
Ground  
WP  
SO  
GND  
GND  
VCC  
WP  
Power Supply  
Write Protect  
Suspends Serial Input  
No Connect  
8-lead SOIC  
CS  
SO  
1
2
3
4
8
7
6
5
VCC  
HOLD  
SCK  
SI  
HOLD  
NC  
WP  
DC  
Don't Connect  
GND  
Rev. 3404D–SEEPR–11/04  
1234567...17

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