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AT25010_03

更新时间: 2024-09-19 04:33:07
品牌 Logo 应用领域
爱特美尔 - ATMEL 可编程只读存储器电动程控只读存储器电可擦编程只读存储器
页数 文件大小 规格书
17页 156K
描述
SPI Serial EEPROMs

AT25010_03 数据手册

 浏览型号AT25010_03的Datasheet PDF文件第2页浏览型号AT25010_03的Datasheet PDF文件第3页浏览型号AT25010_03的Datasheet PDF文件第4页浏览型号AT25010_03的Datasheet PDF文件第5页浏览型号AT25010_03的Datasheet PDF文件第6页浏览型号AT25010_03的Datasheet PDF文件第7页 
Features  
Serial Peripheral Interface (SPI) Compatible  
Supports SPI Modes 0 (0,0) and 3 (1,1)  
Low-voltage and Standard-voltage Operation  
– 2.7 (VCC = 2.7V to 5.5V)  
3.0 MHz Clock Rate (5V)  
8-byte Page Mode  
Block Write Protection  
– Protect 1/4, 1/2, or Entire Array  
Write Protect (WP) Pin and Write Disable Instructions for  
Both Hardware and Software Data Protection  
Self-timed Write Cycle (10 ms max)  
High Reliability  
– Endurance: One Million Write Cycles  
– Data Retention: 100 Years  
Automotive Grade Devices Available  
8-lead PDIP and 8-lead JEDEC SOIC Packages  
SPI Serial  
EEPROMs  
1K (128 x 8)  
2K (256 x 8)  
Description  
4K (512 x 8)  
The AT25010/020/040 provides 1024/2048/4096 bits of serial electrically erasable  
programmable read only memory (EEPROM) organized as 128/256/512 words of 8  
bits each. The device is optimized for use in many industrial and commercial applica-  
tions where low-power and low voltage operation are essential. The AT25010/020/040  
is available in space saving 8-lead PDIP and 8-lead JEDEC SOIC packages.  
AT25010  
AT25020  
AT25040  
The AT25010/020/040 is enabled through the Chip Select pin (CS) and accessed via a  
3-wire interface consisting of Serial Data Input (SI), Serial Data Output (SO), and  
Serial Clock (SCK). All programming cycles are completely self-timed, and no sepa-  
rate ERASE cycle is required before WRITE.  
BLOCK WRITE protection is enabled by programming the status register with one of  
four blocks of write protection. Separate program enable and program disable instruc-  
tions are provided for additional data protection. Hardware data protection is provided  
via the WP pin to protect against inadvertent write attempts. The HOLD pin may be  
used to suspend any serial communication without resetting the serial sequence.  
Pin Configurations  
8-lead PDIP  
Pin Name Function  
CS  
Chip Select  
CS  
SO  
1
2
3
4
8
7
6
5
VCC  
HOLD  
SCK  
SI  
SCK  
SI  
Serial Data Clock  
Serial Data Input  
Serial Data Output  
Ground  
WP  
GND  
SO  
8-lead SOIC  
GND  
VCC  
WP  
CS  
SO  
WP  
1
2
3
4
8
7
6
5
VCC  
HOLD  
SCK  
SI  
Power Supply  
Write Protect  
GND  
HOLD  
Suspends Serial Input  
Rev. 0606M–SEEPR–06/03  

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