May 2005
Preliminary
AS7C4096A
®
5.0V 512K × 8 CMOS SRAM
• Equal access and cycle times
Features
• Easy memory expansion with CE
• TTL-compatible, three-state I/O
• JEDEC standard packages
- 400 mil 36-pin SOJ
- 44-pin TSOP 2
• ESD protection ≥ 2000 volts
• Latch-up current ≥ 200 mA
, OE inputs
• Pin compatible to AS7C4096
• Industrial and commercial temperature
• Organization: 524,288 words × 8 bits
• Center power and ground pins
• High speed
- 10/12/15/20 ns address access time
- 5/6 ns output enable access time
• Low power consumption: ACTIVE
- 880mW/max @ 10 ns
• Low power consumption: STANDBY
- 55mW/max CMOS
Logic block diagram
Pin arrangements
36-pin SOJ (400 mil)
44-pin TSOP 2
VCC
NC
NC
A0
A1
A2
A3
A4
CE
NC
NC
NC
A18
1
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A0
A1
A2
A3
A4
CE
1
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
NC
2
GND
2
A18
A17
3
3
4
Input buffer
4
A16
A15
OE
A17
A16
A15
OE
5
5
6
6
7
A0
A1
A2
I/O1
I/O2
7
I/O8
I/O7
GND
VCC
8
8
I/O1
I/O2
VCC
I/O8
I/O7
9
I/O1
I/O8
VCC
9
10
11
12
13
14
15
16
17
18
19
20
21
22
GND
I/O3
I/O4
WE
A5
10
11
12
13
14
15
16
17
18
524,288 × 8
A3
GND
I/O6
I/O5
A14
A13
A12
A11
A10
NC
VCC
GND
I/O3
I/O4
WE
A5
A4
Array
(4,194,304)
I/O6
I/O5
A14
A13
A12
A11
A10
NC
A5
A6
A7
A8
A9
A6
A7
A6
A8
A7
A9
A8
A9
NC
NC
NC
NC
Column decoder
WE
OE
CE
Control
Circuit
Selection guide
–10
–12
12
–15
–20
Unit
ns
Maximum address access time
Maximum outputenable access time
Maximum operating current
10
5
15
6
20
6
6
ns
160
10
140
10
120
10
100
10
mA
mA
Maximum CMOS standby current
5/27/05, v. 1.1
Alliance Semiconductor
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