AS7C4096A-15JC

更新时间： 2024-11-22 22:53:55

品牌	Logo	应用领域
ALSC		静态存储器
页数	文件大小	规格书
10页	325K
描述
5.0V 512K x 8 CMOS SRAM

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数据手册

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AS7C4096A-15JC 数据手册

May 2005

Preliminary

AS7C4096A

5.0V 512K × 8 CMOS SRAM

• Equal access and cycle times

Features

• Easy memory expansion with CE

• TTL-compatible, three-state I/O

• JEDEC standard packages

- 400 mil 36-pin SOJ

- 44-pin TSOP 2

• ESD protection ≥ 2000 volts

• Latch-up current ≥ 200 mA

, OE inputs

• Pin compatible to AS7C4096

• Industrial and commercial temperature

• Organization: 524,288 words × 8 bits

• Center power and ground pins

• High speed

- 10/12/15/20 ns address access time

- 5/6 ns output enable access time

• Low power consumption: ACTIVE

- 880mW/max @ 10 ns

• Low power consumption: STANDBY

- 55mW/max CMOS

Logic block diagram

Pin arrangements

36-pin SOJ (400 mil)

44-pin TSOP 2

V_CC

A18

GND

A18

A17

Input buffer

A16

A15

A17

A16

A15

I/O1

I/O2

I/O8

I/O7

GND

V_CC

I/O1

I/O2

V_CC

I/O8

I/O7

I/O1

I/O8

V_CC

GND

I/O3

I/O4

524,288 × 8

GND

I/O6

I/O5

A14

A13

A12

A11

A10

V_CC

GND

I/O3

I/O4

Array

(4,194,304)

I/O6

I/O5

A14

A13

A12

A11

A10

Column decoder

Control

Circuit

Selection guide

–10

–12

–15

–20

Unit

Maximum address access time

Maximum outputenable access time

Maximum operating current

160

140

120

100

Maximum CMOS standby current

5/27/05, v. 1.1

Alliance Semiconductor

P. 1 of 10

12 3 4 5 6 7...10

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