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AS7C3364FT32B-10TQIN PDF预览

AS7C3364FT32B-10TQIN

更新时间： 2024-01-10 10:09:45
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
19页 417K
描述
Standard SRAM, 64KX32, 10ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100

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AS7C3364FT32B-10TQIN 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LQFP,针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.52
最长访问时间：10 ns其他特性：FLOW-THROUGH ARCHITECTURE
JESD-30 代码：R-PQFP-G100JESD-609代码：e3
长度：20 mm内存密度：2097152 bit
内存集成电路类型：STANDARD SRAM内存宽度：32
功能数量：1端子数量：100
字数：65536 words字数代码：64000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：64KX32
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：245
认证状态：Not Qualified座面最大高度：1.6 mm
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：MATTE TIN端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：30宽度：14 mm
Base Number Matches：1

AS7C3364FT32B-10TQIN 数据手册

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AS7C3364FT32B  
AS7C3364FT36B  
®
Functional description  
The AS7C3364FT32B/36B is a high-performance CMOS 2-Mbit synchronous Static Random Access Memory (SRAM) device organized as  
65,536 words × 32 or 36 bits.  
Fast cycle times of 7.5/8.5/10/12 ns with clock access times (tCD) of 6.5/7.5/8.0/10 ns. Three chip enable (CE) inputs permit easy memory  
expansion. Burst operation is initiated in one of two ways: the controller address strobe (ADSC), or the processor address strobe (ADSP).  
The burst advance pin (ADV) allows subsequent internally generated burst addresses.  
Read cycles are initiated with ADSP (regardless of WE and ADSC) using the new external address clocked into the on-chip address register  
when ADSP is sampled low, the chip enables are sampled active, and the output buffer is enabled with OE. In a read operation, the data  
accessed by the current address registered in the address registers by the positive edge of CLK are carried to the data-out buffer. ADV is  
ignored on the clock edge that samples ADSP asserted, but is sampled on all subsequent clock edges. Address is incremented internally for  
the next access of the burst when ADV is sampled low and both address strobes are high. Burst mode is selectable with the LBO input. With  
LBO unconnected or driven high, burst operations use an interleaved count sequence. With LBO driven low, the device uses a linear count  
sequence.  
Write cycles are performed by disabling the output buffers with OE and asserting a write command. A global write enable GWE writes all  
32/36 regardless of the state of individual BW[a:d] inputs. Alternately, when GWE is high, one or more bytes may be written by asserting  
BWE and the appropriate individual byte BWn signals.  
BWn is ignored on the clock edge that samples ADSP low, but it is sampled on all subsequent clock edges. Output buffers are disabled when  
BWn is sampled LOW regardless of OE. Data is clocked into the data input register when BWn is sampled low. Address is incremented  
internally to the next burst address if BWn and ADV are sampled low.  
Read or write cycles may also be initiated with ADSC instead of ADSP. The differences between cycles initiated with ADSC and ADSP are  
as follows:  
• ADSP must be sampled high when ADSC is sampled low to initiate a cycle with ADSC.  
• WE signals are sampled on the clock edge that samples ADSC low (and ADSP high).  
• Master chip enable CE0 blocks ADSP, but not ADSC.  
The AS7C3364FT32B and AS7C3364FT36B family operates from a core 3.3V power supply. I/Os use a separate power supply that can  
operate at 2.5V or 3.3V. These devices are available in a 100-pin TQFP package.  
TQFP capacitance  
Parameter  
Input capacitance  
Symbol  
Test conditions  
VIN = 0V  
Min  
Max  
Unit  
pF  
*
CIN  
-
-
5
7
*
I/O capacitance  
CI/O  
VOUT = 0V  
pF  
*Guaranteed not tested  
TQFP thermal resistance  
Description  
Conditions  
Symbol  
Typical  
40  
Units  
°C/W  
°C/W  
1–layer  
4–layer  
θJA  
θJA  
Thermal resistance  
(junction to ambient)1  
Test conditions follow standard test methods and  
procedures for measuring thermal impedance,  
per EIA/JESD51  
22  
Thermal resistance  
θJC  
8
°C/W  
(junction to top of case)1  
1 This parameter is sampled  
2/8/05; v.1.2  
Alliance Semiconductor  
P. 4 of 19  
1234567...19

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与AS7C3364FT32B-10TQIN相关器件

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AS7C3364FT32B-65TQC ALSC 3.3V 64K x 32/36 Flow Through Synchronous SRAM

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AS7C3364FT32B-65TQCN ALSC 3.3V 64K x 32/36 Flow Through Synchronous SRAM

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AS7C3364FT32B-65TQCN ISSI Standard SRAM, 64KX32, 6.5ns, CMOS, PQFP100, 14 X 20 MM, LEAD FREE, TQFP-100

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AS7C3364FT32B-65TQI ALSC 3.3V 64K x 32/36 Flow Through Synchronous SRAM

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AS7C3364FT32B-65TQI ISSI Standard SRAM, 64KX32, 6.5ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100

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AS7C3364FT32B-65TQIN ALSC 3.3V 64K x 32/36 Flow Through Synchronous SRAM

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