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AS7C332MFT18A-75TQC PDF预览

AS7C332MFT18A-75TQC

更新时间： 2024-02-11 11:12:48
品牌 Logo 应用领域
ALSC 内存集成电路静态存储器
页数 文件大小 规格书
19页 512K
描述
3.3V 2M x 18 Flow-through synchronous SRAM

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AS7C332MFT18A-75TQC 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Obsolete零件包装代码：QFP
包装说明：LQFP,针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.51
Is Samacsys：N最长访问时间：7.5 ns
其他特性：FLOW-THROUGH ARCHITECTUREJESD-30 代码：R-PQFP-G100
JESD-609代码：e3长度：20 mm
内存密度：37748736 bit内存集成电路类型：STANDARD SRAM
内存宽度：18功能数量：1
端子数量：100字数：2097152 words
字数代码：2000000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：2MX18封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：245认证状态：Not Qualified
座面最大高度：1.6 mm最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：MATTE TIN
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：14 mmBase Number Matches：1

AS7C332MFT18A-75TQC 数据手册

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AS7C332MFT18A  
®
Signal descriptions  
Description  
Pin  
CLK  
I/O Properties  
I
I
CLOCK  
SYNC  
SYNC  
Clock. All inputs except OE, ZZ, and LBO are synchronous to this clock.  
Address. Sampled when all chip enables are active and when ADSC or ADSP are asserted.  
Data. Driven as output when the chip is enabled and when OE is active.  
A,A0,A1  
DQ[a,b]  
I/O  
Master chip enable. Sampled on clock edges when ADSP or ADSC is active. When CE0 is inactive,  
ADSP is blocked. Refer to the “Synchronous truth table” for more information.  
CE0  
I
I
SYNC  
SYNC  
Synchronous chip enables, active high, and active low, respectively. Sampled on clock edges when  
ADSC is active or when CE0 and ADSP are active.  
CE1, CE2  
ADSP  
ADSC  
ADV  
I
I
I
SYNC  
SYNC  
SYNC  
Address strobe processor. Asserted low to load a new address or to enter standby mode.  
Address strobe controller. Asserted low to load a new address or to enter standby mode.  
Advance. Asserted low to continue burst read/write.  
Global write enable. Asserted low to write all 18 bits. When high, BWE and BW[a,b] control write  
enable.  
GWE  
BWE  
I
I
SYNC  
SYNC  
Byte write enable. Asserted low with GWE high to enable effect of BW[a,b] inputs.  
Write enables. Used to control write of individual bytes when GWE is high and BWE is low. If any of  
BW[a,b] is active with GWE high and BWE low, the cycle is a write cycle. If all BW[a,b] are inactive,  
the cycle is a read cycle.  
BW[a,b]  
I
SYNC  
OE  
I
I
ASYNC  
STATIC  
Asynchronous output enable. I/O pins are driven when OE is active and chip is in read mode.  
Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When  
driven Low, device follows linear Burst order. This signal is internally pulled High.  
LBO  
ZZ  
I
-
ASYNC  
-
Snooze. Places device in low power mode; data is retained. Connect to GND if unused.  
No connect  
NC  
Snooze Mode  
SNOOZE MODE is a low current, power-down mode in which the device is deselected and current is reduced to ISB2. The duration of  
SNOOZE MODE is dictated by the length of time the ZZ is in a High state.  
The ZZ pin is an asynchronous, active high input that causes the device to enter SNOOZE MODE.  
When the ZZ pin becomes a logic High, ISB2 is guaranteed after the time tZZI is met. After entering SNOOZE MODE, all inputs except ZZ is  
disabled and all outputs go to High-Z. Any operation pending when entering SNOOZE MODE is not guaranteed to successfully complete.  
Therefore, SNOOZE MODE (READ or WRITE) must not be initiated until valid pending operations are completed. Similarly, when exiting  
SNOOZE MODE during tPUS, only a DESELECT or READ cycle should be given while the SRAM is transitioning out of SNOOZE MODE.  
12/23/04, v 1.3  
Alliance Semiconductor  
5 of 19  
12345678...19

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