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AS7C332MNTD18A-167BIN PDF预览

AS7C332MNTD18A-167BIN

更新时间: 2024-02-01 07:51:11
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
22页 452K
描述
ZBT SRAM, 2MX18, 7.5ns, CMOS, PBGA165, LEAD FREE, BGA-165

AS7C332MNTD18A-167BIN 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:BGA
包装说明:LBGA,针数:165
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.51
最长访问时间:7.5 ns其他特性:FLOW-THROUGH OR PIPELINED ARCHITECTURE
JESD-30 代码:R-PBGA-B165JESD-609代码:e3
长度:17 mm内存密度:37748736 bit
内存集成电路类型:ZBT SRAM内存宽度:18
功能数量:1端子数量:165
字数:2097152 words字数代码:2000000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:2MX18
封装主体材料:PLASTIC/EPOXY封装代码:LBGA
封装形状:RECTANGULAR封装形式:GRID ARRAY, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):250
认证状态:Not Qualified座面最大高度:1.46 mm
最大供电电压 (Vsup):3.465 V最小供电电压 (Vsup):3.135 V
标称供电电压 (Vsup):3.3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:BALL
端子节距:1 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:40宽度:15 mm
Base Number Matches:1

AS7C332MNTD18A-167BIN 数据手册

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April 2004  
AS7C332MNTD18A  
®
3.3V 2M × 18 SRAM with NTDTM  
• Common data inputs and data outputs  
Features  
• Asynchronous output enable control  
• Available in 100-pin TQFP and 165-ball BGA packages  
• Byte write enables  
• Clock enable for operation hold  
• Multiple chip enables for easy expansion  
• 3.3V core power supply  
• Organization: 2,097,152 words × 18 bits  
• NTD™1 architecture for efficient bus operation  
• Fast clock speeds to 200 MHz in LVTTL/LVCMOS  
• Fast clock to data access: 3.1/3.4/3.8 ns  
• Fast OE access time: 3.1/3.4/3.8 ns  
• Fully synchronous operation  
• 2.5V or 3.3V I/O operation with separate VDDQ  
• Self-timed write cycles  
• Flow-through or pipelined mode  
• Interleaved or linear burst modes  
• Snooze mode for standby operation  
• Boundary scan using IEEE 1149.1 JTAG function  
1. NTD™ is a trademark of Alliance Semiconductor Corporation. All trade-  
marks mentioned in this document are the property of their respective owners.  
Logic block diagram  
21  
21  
Q
A[20:0]  
D
Address  
register  
Burst logic  
CLK  
D
Q
CE0  
CE1  
CE2  
Write delay  
addr. registers  
21  
CLK  
R/W  
BWa  
Control  
logic  
CLK  
BWb  
ADV / LD  
FT  
LBO  
ZZ  
2 M x 18  
SRAM  
Array  
CLK  
18  
18  
DQ[a,b]  
Data  
Input  
Register  
D
Q
18  
18  
CLK  
18  
CLK  
CEN  
CLK  
Output  
Register  
OE  
18  
OE  
DQ[a,b]  
Selection guide  
-200  
5
-167  
6
-133  
7.5  
Units  
ns  
Minimum cycle time  
Maximum pipelined clock frequency  
Maximum pipelined clock access time  
Maximum operating current  
200  
3.1  
400  
120  
70  
167  
3.4  
350  
110  
70  
133  
3.8  
MHz  
ns  
325  
100  
70  
mA  
mA  
mA  
Maximum standby current  
Maximum CMOS standby current (DC)  
4/26/04, V 1.2  
Alliance Semiconductor  
P. 1 of 22  
Copyright © Alliance Semiconductor. All rights reserved.  

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