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AS7C331MPFS18A-250BI PDF预览

AS7C331MPFS18A-250BI

更新时间: 2024-11-04 03:03:07
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器
页数 文件大小 规格书
21页 414K
描述
Standard SRAM, 1MX18, 6.5ns, CMOS, PBGA165, BGA-165

AS7C331MPFS18A-250BI 数据手册

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August 2002  
Advance Information  
AS7C331MPFS18A  
®
1M x 18 pipelined burst synchronous SRAM  
Features  
• Organization: 1,048,576 x18 bits  
Available 100-pin TQFP and 165-ball BGA packages  
Byte write enables  
• Multiple chip enables for easy expansion  
• 3.3V core power supply  
• 2.5V or 3.3V I/ O operation with separate VDDQ  
• NTD™ pipelined architecture available (AS7C331MNTD18A,  
AS7C33512NTD32A/ AS7C33512NTD36A)  
Fast clock speeds to 250MHz in LVTTL/ LVCMOS  
Fast clock to data access: 2.6/ 2.8/ 3/ 3.4 ns  
Fast OEaccess time: 2.6/ 2.8/ 3/ 3.4 ns  
Fully synchronous register-to-register operation  
Single register flow-through mode  
Single-cycle deselect  
Asynchronous output enable control  
Logic block diagram  
LBO  
CLK  
ADV  
CLK  
CS  
CLR  
ADSC  
ADSP  
Burst logic  
20 18  
1M 18  
Memory  
array  
20  
20  
AddresQs  
register  
D
A[19:0]  
CS  
CLK  
18  
18  
2
GWE  
D
Q
DQb  
BW  
b
Byte Write  
registers  
BWE  
CLK  
D
Q
DQa  
BW  
Byte Write  
CLK  
a
registers  
CE0  
CE1  
CE2  
OE  
DEnableQ  
register  
Input  
Output  
registers  
registers  
CE  
CLK  
CLK  
CLK  
DEnableQ  
Power  
down  
delay  
ZZ  
register  
CLK  
OE  
18  
DQ[a,b]  
FT  
Selection guide  
-250  
4
-225  
-200  
5
-166  
6
Units  
ns  
Minimum cycle time  
4.4  
225  
2.8  
400  
110  
70  
Maximum clock frequency  
250  
2.6  
425  
110  
70  
200  
3.0  
370  
110  
70  
166  
3.4  
340  
90  
MHz  
ns  
Maximum pipelined clock access time  
Maximum operating current  
Maximum standby current  
mA  
mA  
mA  
Maximum CMOS standby current (DC)  
9/ 5/ 02; v. 0.9.1 Advance Info  
70  
Alliance Semiconductor  
1 of 21  
Copyright © Alliance Semiconductor. All rights reserved.  

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