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AS7C331MPFS18A-250TQC PDF预览

AS7C331MPFS18A-250TQC

更新时间: 2024-11-29 14:47:47
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
21页 411K
描述
Standard SRAM, 1MX18, 6.5ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100

AS7C331MPFS18A-250TQC 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:QFP
包装说明:LQFP,针数:100
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.63
Is Samacsys:N最长访问时间:6.5 ns
其他特性:FLOW-THROUGH OR PIPELINED ARCHITECTUREJESD-30 代码:R-PQFP-G100
JESD-609代码:e0长度:20 mm
内存密度:18874368 bit内存集成电路类型:STANDARD SRAM
内存宽度:18功能数量:1
端子数量:100字数:1048576 words
字数代码:1000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:1MX18封装主体材料:PLASTIC/EPOXY
封装代码:LQFP封装形状:RECTANGULAR
封装形式:FLATPACK, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED认证状态:Not Qualified
座面最大高度:1.6 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3.135 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.65 mm
端子位置:QUAD处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:14 mmBase Number Matches:1

AS7C331MPFS18A-250TQC 数据手册

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December 2002  
Advance Information  
AS7C331MPFS18A  
®
1M x 18 pipelined burst synchronous SRAM  
Features  
• Organization: 1,048,576 x18 bits  
Available 100-pin TQFP and 165-ball BGA packages  
Byte write enables  
• Multiple chip enables for easy expansion  
• 3.3V core power supply  
• 2.5V or 3.3V I/ O operation with separate VDDQ  
• NTD™ pipelined architecture available (AS7C331MNTD18A,  
AS7C33512NTD32A/ AS7C33512NTD36A)  
Fast clock speeds to 250MHz in LVTTL/ LVCMOS  
Fast clock to data access: 2.6/ 2.8/ 3/ 3.4 ns  
Fast OEaccess time: 2.6/ 2.8/ 3/ 3.4 ns  
Fully synchronous register-to-register operation  
Single register flow-through mode  
Single-cycle deselect  
Asynchronous output enable control  
Logic block diagram  
LBO  
CLK  
ADV  
CLK  
CS  
CLR  
ADSC  
ADSP  
Burst logic  
20 18  
1M 18  
Memory  
array  
20  
20  
AddresQs  
register  
D
A[19:0]  
CS  
CLK  
18  
18  
2
GWE  
D
Q
DQb  
BW  
b
Byte Write  
registers  
BWE  
CLK  
D
Q
DQa  
BW  
Byte Write  
CLK  
a
registers  
CE0  
CE1  
CE2  
OE  
DEnableQ  
register  
Input  
Output  
registers  
registers  
CE  
CLK  
CLK  
CLK  
DEnableQ  
Power  
down  
delay  
ZZ  
register  
CLK  
OE  
18  
DQ[a,b]  
FT  
Selection guide  
-250  
4
-225  
-200  
5
-166  
6
Units  
ns  
Minimum cycle time  
4.4  
225  
2.8  
400  
110  
70  
Maximum clock frequency  
250  
2.6  
425  
110  
70  
200  
3.0  
370  
110  
70  
166  
3.4  
340  
90  
MHz  
ns  
Maximum pipelined clock access time  
Maximum operating current  
Maximum standby current  
mA  
mA  
mA  
Maximum CMOS standby current (DC)  
12/ 2/ 02, v. 0.9.2 Advance Info  
70  
Alliance Semiconductor  
1 of 21  
Copyright © Alliance Semiconductor. All rights reserved.  

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