Datasheet > 存储 > SRAM> AS7C251MPFS36A-200TQC

AS7C251MPFS36A-200TQC

更新时间： 2024-11-29 23:00:31

品牌	Logo	应用领域
ALSC		存储内存集成电路静态存储器时钟
页数	文件大小	规格书
19页	523K
描述
2.5V 1M x 32/36 pipelined burst synchronous SRAM

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AS7C251MPFS36A-200TQC 数据手册

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February 2005

AS7C251MPFS32A

AS7C251MPFS36A

2.5V 1M × 32/36 pipelined burst synchronous SRAM

Features

• Individual byte write and global write

• Multiple chip enables for easy expansion

• 2.5V core power supply

• Linear or interleaved burst control

• Snooze mode for reduced power-standby

• Common data inputs and data outputs

• Organization: 1,048,576 words × 32 or 36 bits

• Fast clock speeds to 200 MHz

• Fast clock to data access: 3.1/3.5/3.8 ns

• Fast OE access time: 3.1/3.5/3.8 ns

• Fully synchronous register-to-register operation

• Single-cycle deselect

• Asynchronous output enable control

• Available in 100-pin TQFP package

Logic block diagram

LBO

CLK

ADV

ADSC

ADSP

CLK

CLR

Burst logic

1M × 32/36

Memory

array

CLK

A[19:0]

Address

32/36

GWE

BWE

BW_d

DQ_d

Byte write

registers

CLK

DQ_c

Byte write

registers

BW_c

BW_b

CLK

DQ_b

Byte write

registers

CLK

DQ_a

Byte write

registers

BW_a

CLK

CE0

CE1

Output

registers

CE2

Input

registers

CLK

Enable

CLK

Enable

Power

down

delay

CLK

32/36

DQ[a:d]

Selection guide

-200

-166

-133

7.5

Units

Minimum cycle time

Maximum clock frequency

Maximum clock access time

Maximum operating current

Maximum standby current

200

3.1

450

170

166

3.5

400

150

133

3.8

MHz

350

140

Maximum CMOS standby current (DC)

2/14/05, v.1.3

Alliance Semiconductor

1 of 19

12 3 4 5 6 7...19

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