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AS7C252MFT18A-75BCN PDF预览

AS7C252MFT18A-75BCN

更新时间: 2024-11-27 21:10:31
品牌 Logo 应用领域
ALSC 时钟ISM频段静态存储器内存集成电路
页数 文件大小 规格书
23页 561K
描述
Standard SRAM, 2MX18, 7.5ns, CMOS, PBGA165, LEAD FREE, BGA-165

AS7C252MFT18A-75BCN 数据手册

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April 2004  
AS7C252MFT18A  
®
2.5V 2M × 18 Flow-through synchronous SRAM  
Features  
• Organization: 2,097152 words × 18 bits  
• Fast clock to data access: 6.5/7.5/8.5 ns  
• Fast OE access time: 3.5/3.5/4.0 ns  
• Fully synchronous flow-through operation  
• Asynchronous output enable control  
• Available in 100-pin TQFP package and 165-ball BGA  
• Individual byte write and global write  
• Multiple chip enables for easy expansion  
• 2.5V core power supply  
• Common data inputs and data outputs  
• Boundary scan using IEEE 1149.1 JTAG function  
1
• NTD™ pipelined architecture available  
(AS7C252MNTD18A, AS7C251MNTD32A/  
AS7C251MNTD36A)  
1 NTD™ is a trademark of Alliance Semiconductor Corporation. All  
trademarks mentioned in this document are the property of their  
respective owners.  
• Linear or interleaved burst control  
• Snooze mode for reduced power-standby  
Logic block diagram  
LBO  
CLK  
CLK  
CS  
ADV  
ADSC  
ADSP  
Burst logic  
2M x 18  
CLR  
Memory  
array  
21 19  
21  
21  
Q
D
A[20:0]  
Address  
CS  
register  
CLK  
18  
18  
2
GWE  
BWb  
D
DQb  
Q
Byte Write  
registers  
BWE  
BWa  
CLK  
D
Q
DQa  
Byte Write  
registers  
CLK  
CE0  
CE1  
OE  
Output  
D
Q
Q
Input  
registers  
Enable  
register  
CE  
CLK  
CE2  
registers  
CLK  
CLK  
D
Enable  
delay  
register  
CLK  
Power  
down  
ZZ  
OE  
18  
DQ[a,b]  
Selection guide  
-65  
7.5  
-75  
8.5  
-85  
10  
Units  
ns  
Minimum cycle time  
Maximum clock access time  
Maximum operating current  
Maximum standby current  
6.5  
7.5  
8.5  
270  
130  
110  
ns  
310  
140  
110  
290  
130  
110  
mA  
mA  
mA  
Maximum CMOS standby current (DC)  
4/26/04, v 1.0  
Alliance Semiconductor  
1 of 23  
Copyright © Alliance Semiconductor. All rights reserved.  

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