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AS7C252MFT18A-85TQCN

更新时间： 2024-11-23 22:35:35

品牌	Logo	应用领域
ALSC		静态存储器
页数	文件大小	规格书
19页	509K
描述
2.5V 2M x 18 Flow-through synchronous SRAM

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AS7C252MFT18A-85TQCN 数据手册

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January 2005

AS7C252MFT18A

2.5V 2M × 18 Flow-through synchronous SRAM

Features

• Organization: 2,097152 words × 18 bits

• Fast clock to data access: 7.5/8.5/10 ns

• Fast OE access time: 3.5/4.0 ns

• Fully synchronous flow-through operation

• Asynchronous output enable control

• Available in 100-pin TQFP package

• Individual byte write and global write

• Multiple chip enables for easy expansion

• 2.5V core power supply

• Linear or interleaved burst control

• Snooze mode for reduced power-standby

• Common data inputs and data outputs

Logic block diagram

LBO

CLK

ADV

ADSC

ADSP

CLK

Burst logic

2M x 18

CLR

Memory

array

21 19

A[20:0]

Address

CLK

GWE

BW_b

DQb

Byte Write

registers

BWE

BW_a

CLK

DQa

Byte Write

registers

CLK

CE0

CE1

Output

Input

registers

Enable

CLK

CE2

registers

CLK

Enable

delay

CLK

Power

down

DQ[a,b]

Selection guide

-75

8.5

7.5

325

130

-85

-10

Units

Minimum cycle time

Maximum clock access time

Maximum operating current

Maximum standby current

Maximum CMOS standby current (DC)

8.5

300

130

275

130

1/17/05, v 1.2

Alliance Semiconductor

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12 3 4 5 6 7...19

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