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AS7C251MNTD36A-133BCN PDF预览

AS7C251MNTD36A-133BCN

更新时间: 2024-10-29 03:24:43
品牌 Logo 应用领域
ALSC 静态存储器
页数 文件大小 规格书
22页 453K
描述
ZBT SRAM, 1MX36, 10ns, CMOS, PBGA165, LEAD-FREE, BGA-165

AS7C251MNTD36A-133BCN 数据手册

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AS7C251MNTD32A  
AS7C251MNTD36A  
®
Signal descriptions  
Signal  
CLK  
I/O Properties Description  
I
I
I
CLOCK Clock. All inputs except OE, FT, LBO, and ZZ are synchronous to this clock.  
CEN  
SYNC  
SYNC  
SYNC  
Clock enable. When de-asserted high, the clock input signal is masked.  
Address. Sampled when all chip enables are active and ADV/LD is asserted.  
Data. Driven as output when the chip is enabled and OE is active.  
A, A0, A1  
DQ[a,b,c,d] I/O  
CE0, CE1,  
CE2  
Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted.  
Are ignored when ADV/LD is high.  
I
SYNC  
Advance or Load. When sampled high, the internal burst address counter will increment in  
the order defined by the LBO input value. (refer to table on page 2) When low, a new  
address is loaded.  
ADV/LD  
R/W  
I
I
SYNC  
A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE  
operation. Is ignored when ADV/LD is high.  
SYNC  
SYNC  
Byte write enables. Used to control write on individual bytes. Sampled along with WRITE  
command and BURST WRITE.  
BW[a,b,c,d]  
OE  
I
I
I
ASYNC Asynchronous output enable. I/O pins are not driven when OE is inactive.  
Selects Burst mode. When tied to VDD or left floating, device follows interleaved Burst order. When  
STATIC  
LBO  
driven Low, device follows linear Burst order. This signal is internally pulled High.  
Selects Pipeline or Flow-through mode. When tied to VDD or left floating, enables Pipeline mode.  
STATIC  
FT  
I
When driven Low, enables single register Flow-through mode. This signal is internally pulled High.  
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. (BGA  
TDO  
TDI  
O
I
SYNC  
only)  
SYNC  
Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. (BGA only)  
This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.  
(BGA only)  
TMS  
I
SYNC  
Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. (BGA  
only)  
TCK  
O
SYNC  
ZZ  
I
-
ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused.  
No connects.  
NC  
-
4/26/04, V 1.0  
Alliance Semiconductor  
P. 5 of 22  

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