Datasheet > AS7C251MNTD36A-133BCN

AS7C251MNTD36A-133BCN

更新时间： 2024-10-29 03:24:43

品牌	Logo	应用领域
ALSC		静态存储器
页数	文件大小	规格书
22页	453K
描述
ZBT SRAM, 1MX36, 10ns, CMOS, PBGA165, LEAD-FREE, BGA-165

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

AS7C251MNTD36A-133BCN 数据手册

浏览型号AS7C251MNTD36A-133BCN的Datasheet PDF文件第2页

浏览型号AS7C251MNTD36A-133BCN的Datasheet PDF文件第3页

浏览型号AS7C251MNTD36A-133BCN的Datasheet PDF文件第4页

浏览型号AS7C251MNTD36A-133BCN的Datasheet PDF文件第6页

浏览型号AS7C251MNTD36A-133BCN的Datasheet PDF文件第7页

浏览型号AS7C251MNTD36A-133BCN的Datasheet PDF文件第8页

AS7C251MNTD32A

AS7C251MNTD36A

Signal descriptions

Signal

CLK

I/O Properties Description

CLOCK Clock. All inputs except OE, FT, LBO, and ZZ are synchronous to this clock.

CEN

SYNC

Clock enable. When de-asserted high, the clock input signal is masked.

Address. Sampled when all chip enables are active and ADV/LD is asserted.

Data. Driven as output when the chip is enabled and OE is active.

A, A0, A1

DQ[a,b,c,d] I/O

CE0, CE1,

CE2

Synchronous chip enables. Sampled at the rising edge of CLK, when ADV/LD is asserted.

Are ignored when ADV/LD is high.

SYNC

Advance or Load. When sampled high, the internal burst address counter will increment in

the order defined by the LBO input value. (refer to table on page 2) When low, a new

address is loaded.

ADV/LD

R/W

SYNC

A high during LOAD initiates a READ operation. A low during LOAD initiates a WRITE

operation. Is ignored when ADV/LD is high.

SYNC

Byte write enables. Used to control write on individual bytes. Sampled along with WRITE

command and BURST WRITE.

BW[a,b,c,d]

ASYNC Asynchronous output enable. I/O pins are not driven when OE is inactive.

Selects Burst mode. When tied to V_DDor left floating, device follows interleaved Burst order. When

STATIC

LBO

driven Low, device follows linear Burst order. This signal is internally pulled High.

Selects Pipeline or Flow-through mode. When tied to V_DDor left floating, enables Pipeline mode.

STATIC

When driven Low, enables single register Flow-through mode. This signal is internally pulled High.

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. (BGA

TDO

TDI

SYNC

only)

SYNC

Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. (BGA only)

This pin controls the Test Access Port state machine. Sampled on the rising edge of TCK.

(BGA only)

TMS

SYNC

Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK. (BGA

only)

TCK

SYNC

ASYNC Snooze. Places device in low power mode; data is retained. Connect to GND if unused.

No connects.

4/26/04, V 1.0

Alliance Semiconductor

P. 5 of 22

1 2 3 456 7 8...22

中文翻译

下载PDF

与AS7C251MNTD36A-133BCN相关器件

型号	品牌	获取价格	描述	数据表
AS7C251MNTD36A-133BI	ALSC	获取价格	ZBT SRAM, 1MX36, 10ns, CMOS, PBGA165, BGA-165
AS7C251MNTD36A-133BIN	ALSC	获取价格	ZBT SRAM, 1MX36, 10ns, CMOS, PBGA165, LEAD-FREE, BGA-165
AS7C251MNTD36A-133TQC	ALSC	获取价格	2.5V 1M x 32/36 Pipelined SRAM with NTD
AS7C251MNTD36A-133TQC	ISSI	获取价格	ZBT SRAM, 1MX36, 3.8ns, CMOS, PQFP100, 14 X 20 MM, TQFP-100
AS7C251MNTD36A-133TQCN	ALSC	获取价格	2.5V 1M x 32/36 Pipelined SRAM with NTD
AS7C251MNTD36A-133TQCN	ISSI	获取价格	ZBT SRAM, 1MX36, 3.8ns, CMOS, PQFP100, 14 X 20 MM, LEAD-FREE, TQFP-100
AS7C251MNTD36A-133TQI	ALSC	获取价格	2.5V 1M x 32/36 Pipelined SRAM with NTD
AS7C251MNTD36A-133TQIN	ISSI	获取价格	ZBT SRAM, 1MX36, 3.8ns, CMOS, PQFP100, 14 X 20 MM, LEAD-FREE, TQFP-100
AS7C251MNTD36A-133TQIN	ALSC	获取价格	2.5V 1M x 32/36 Pipelined SRAM with NTD
AS7C251MNTD36A-166TQC	ALSC	获取价格	2.5V 1M x 32/36 Pipelined SRAM with NTD

与AS7C251MNTD36A-133BCN相关文章

三星深化印度制造布局，供应链本地化进程加速
2024-10-29

12
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

11
纳微科技震撼发布GaNSlim革新氮化镓功率芯片
2024-10-18

39
意法半导体发布第四代SiC技术，助力电动汽车电驱
2024-10-15

46

产品中心

服务支持

精选活动

关于我们

帮助中心

AS7C251MNTD36A-133BCN

AS7C251MNTD36A-133BCN 数据手册

与AS7C251MNTD36A-133BCN相关器件

与AS7C251MNTD36A-133BCN相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

AS7C251MNTD36A-133BCN

AS7C251MNTD36A-133BCN 数据手册

与AS7C251MNTD36A-133BCN相关器件

与AS7C251MNTD36A-133BCN相关文章

您还可以找

您在本页遇到什么问题？