Datasheet > 存储 > DRAM> AS4LC4M16S0-75TC

AS4LC4M16S0-75TC

更新时间： 2024-02-14 12:25:51

品牌	Logo	应用领域
ALSC		存储内存集成电路光电二极管动态存储器
页数	文件大小	规格书
24页	548K
描述
3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM

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AS4LC4M16S0-75TC 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	TSOP2	包装说明：	TSOP2,
针数：	54	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.32.00.02
风险等级：	5.28	Is Samacsys：	N
访问模式：	FOUR BANK PAGE BURST	最长访问时间：	5.4 ns
其他特性：	AUTO/SELF REFRESH	JESD-30 代码：	R-PDSO-G54
长度：	22.22 mm	内存密度：	67108864 bit
内存集成电路类型：	SYNCHRONOUS DRAM	内存宽度：	16
功能数量：	1	端口数量：	1
端子数量：	54	字数：	4194304 words
字数代码：	4000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	4MX16	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSOP2	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE, THIN PROFILE	认证状态：	Not Qualified
座面最大高度：	1.2 mm	自我刷新：	YES
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子形式：	GULL WING	端子节距：	0.8 mm
端子位置：	DUAL	宽度：	10.16 mm
Base Number Matches：	1

AS4LC4M16S0-75TC 数据手册

AS4LC4M16S0

AS4LC16M4S0

Functional description

The AS4LC8M8S0 and AS4LC4M16S0 are high-performance 64-megabit CMOS Synchronous Dynamic Random Access

Memory (SDRAM) devices organized as 2,097,152 words × 8 bits × 4 banks, and 1,048,576 words × 16 bits × 4 banks,

respectively. Very high bandwidth is achieved using a pipelined architecture where all inputs and outputs are referenced to the

rising edge of a common clock. Programmable burst mode can be used to read up to a full page of data without selecting a

new column address.

The four internal banks can be alternately accessed (read or write) at the maximum clock frequency for seamless interleaving

operations. This provides a significant advantage over asynchronous EDO and fast page mode devices.

This SDRAM product also features a programmable mode register, allowing users to select read latency as well as burst length

and type (sequential or interleaved). Lower latency improves first data access in terms of CLK cycles, while higher latency

improves maximum frequency of operation. This feature enables flexible performance optimization for a variety of

applications.

DRAM commands and functions are decoded from control inputs. Basic commands are as follows:

• Deactivate all banks

• Select row; activate bank

• CBR refresh

• Mode register set

• Deactivate bank

• Deselect; power down

• Select column; write

• Select column; read

• Auto precharge with read/ write • Self-refresh

The 64 Mb DRAM devices are available in 400-mil plastic TSOP II packages and have 54 pins in each configuration. Both

devices operate with a power supply of 3.3V ± 0.3V. Multiple power and ground pins are provided for low switching noise

and EMI. Inputs and outputs are LVTTL-compatible.

Logic block diagram

CLK

Clock generator

CKE

BA0, BA1

Bank select

A[11:0]

Row

address

buffer

†

Bank A 1M×16

(4096×256×16)

†

Bank B 1M×16

(4096×256×16)

Mode register

Bank C^†1M×16

(4096×256×16)

Refresh

counter

Bank D^†1M×16

(4096×256×16)

Sense amplifier

‡

Column decoder and

latch circuit

DQM

Column

address

buffer

RAS

CAS

Data control circuit

Burst

counter

†

‡

For AS4LC8M8S0, Banks A-D will read 8M×8 (4096×512×8).

For AS4LC4M16S0, DQM will be UDQM and LDQM.

ALLIANCE SEMICONDUCTOR

7/ 5/ 00

123 4 5 6 7...24

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与AS4LC4M16S0-75TC相关器件

型号	品牌	描述	获取价格	数据表
AS4LC4M16S0-8TC	ALSC	3.3V 4Mx16 and 8Mx8 CMOS synchronous DRAM	获取价格
AS4LC4M16SO-10TC	ALSC	DRAM	获取价格
AS4LC4M16SO-8TC	ALSC	DRAM	获取价格
AS4LC4M4	AUSTIN	4M x 4 CMOS DRAM WITH FAST PAGE MODE, 3.3V	获取价格
AS4LC4M4883C	AUSTIN	4 MEG x 4 DRAM 3.3V, EDO PAGE MODE	获取价格
AS4LC4M4DG-6/IT	AUSTIN	4M x 4 CMOS DRAM WITH FAST PAGE MODE, 3.3V	获取价格

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