Datasheet > AS4LC2M8S0-12

AS4LC2M8S0-12

更新时间： 2024-01-11 09:44:09

品牌	Logo	应用领域
ALSC		动态存储器
页数	文件大小	规格书
26页	576K
描述
DRAM

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技术参数
数据手册

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AS4LC2M8S0-12 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	TSOP2	包装说明：	TSOP2, TSOP44,.46,32
针数：	44	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.32.00.02
风险等级：	5.92	访问模式：	DUAL BANK PAGE BURST
最长访问时间：	8.5 ns	其他特性：	AUTO/SELF REFRESH
最大时钟频率 (fCLK)：	83 MHz	I/O 类型：	COMMON
交错的突发长度：	1,2,4,8	JESD-30 代码：	R-PDSO-G44
JESD-609代码：	e0	长度：	18.41 mm
内存密度：	16777216 bit	内存集成电路类型：	SYNCHRONOUS DRAM
内存宽度：	8	功能数量：	1
端口数量：	1	端子数量：	44
字数：	2097152 words	字数代码：	2000000
工作模式：	SYNCHRONOUS	最高工作温度：	70 °C
最低工作温度：		组织：	2MX8
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	TSOP2	封装等效代码：	TSOP44,.46,32
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE, THIN PROFILE
峰值回流温度（摄氏度）：	240	电源：	3.3 V
认证状态：	Not Qualified	刷新周期：	4096
座面最大高度：	1.2 mm	自我刷新：	YES
连续突发长度：	1,2,4,8,FP	最大待机电流：	0.002 A
子类别：	DRAMs	最大压摆率：	0.11 mA
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.8 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	10.16 mm
Base Number Matches：	1

AS4LC2M8S0-12 数据手册

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Command

Pin settings

Description

The following sequence is recommended prior to normal operation.

1. Apply power, start clock, and assert CKE and DQM high. All other signals

are NOP.

2. After power-up, pause for a minimum of 200µs. CKE/ DQM = high; all oth-

ers NOP.

Power up

3. Precharge both banks.

4. Perform Mode Register Set command to initialize mode register.

5. Perform a minimum of 8 auto refresh cycles to stabilize internal circuitry.

(Steps 4 and 5 may be interchanged.)

The mode register stores the user selected opcode for the SDRAM operating

modes. The CAS latency, burst length, burst type, test mode and other vendor

specific functions are selected/ programmed during the Mode Register Set

command cycle. The default setting of the mode register is not defined after

power-up. Therefore, it is recommended that the power-up and mode register

set cycle be executed prior to normal SDRAM operation. Refer to the Mode

Moderegister CS = RAS = CAS = WE =

set

low; A0~A11 = opcode

The SDRAM performs a "no operation" (NOP) when RAS, CAS, and WE = high.

Since the NOP performs no operation, itmay be used as a wait state in

performing normal SDRAM functions. The SDRAM is deselected when CS is

high. CS high disables the command decoder such that RAS, CAS, WE and

address inputs are ignored. Device deselection is also considered a NOP.

Device

deselect and CS = high

no operation

CS = RAS = low; CAS = WE The SDRAM is configured with two internal banks. Use the Bank Activate

= high; A0~A10 = row command to select a row in one of the two idle banks. Initiate a read or write

address; A11 = bank select operation after t_RCD(min) from the time of bank activation.

Bank

activation

Use the Burst Read command to access a consecutive burst of data from an

CS = CAS = A10 = low;

active row in an active bank. Burst read can be initiated on any column address

RAS = WE = high; A11 =

of an active row. The burst length, sequence and latency are determined by the

bank select, A0~A8 =

mode register setting. The first output data appears after the CAS latency from

column address; (A9 =

Burst read

the read command. The output goes into a high impedance state at the end of

don’t care for 2M×8;

the burst (BL = 1,2,4,8) unless a new burst read is initiated to form a gapless

A8,A9 = don’t care for

output data stream. Terminate the burst with a burst stop command, precharge

1M×16)

command to the same bank or another burst read/ write

CS = CAS = WE = A10 =

Use the Burst Write command to write data into the SDRAM on consecutive

low; RAS = high; A0~A9 = clock cycles to adjacent column addresses. The burst length and addressing

column address; (A9 =

don’t care for 2M×8;

A8,A9 = don’t care for

1M×16)

mode is determined by the mode register opcode. Input the initial write address

in the same clock cycle as the Burst Write command. Terminate the burst with a

burst stop command, precharge command to the same bank or another burst

read/ write. DQM can also be used to mask the input data.

Burst write

Use DQM to mask input and output data. It disables the output buffers in a read

operation and masks input data in a write operation. The output data is invalid 2

clocks after DQM assertion (2 clock latency). Input data is masked on the same

clock as DQM assertion (0 clock latency).

DQM

operation

CS = WE = low; RAS = CAS Use burst stop to terminate burst operation. This command may be used to

Burst stop

= high

terminate all legal burst lengths.

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与AS4LC2M8S0-12相关器件

型号	品牌	描述	获取价格	数据表
AS4LC2M8S0-12TC	ALSC	Synchronous DRAM, 2MX8, 8.5ns, CMOS, PDSO44, 0.400 INCH, PLASTIC, TSOP2-44	获取价格
AS4LC2M8S0-15TC	ETC	x8 SDRAM	获取价格
AS4LC2M8S0-7TC	ALSC	3.3V 2M × 8/1M × 16 CMOS synchronous DRAM	获取价格
AS4LC2M8S0-8	ALSC	DRAM	获取价格
AS4LC2M8S0-8TC	ALSC	3.3V 2M × 8/1M × 16 CMOS synchronous DRAM	获取价格
AS4LC2M8S1	ALSC	3.3V 2M x 8/1M x 16 CMOS synchronous DRAM	获取价格

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