Datasheet > AS4C1M16F5

AS4C1M16F5

更新时间： 2022-11-24 21:43:16

品牌	Logo	应用领域
其他 - ETC		动态存储器
页数	文件大小	规格书
21页	475K
描述
5V 1M X 16 CMOS DRAM

阅读下载

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

AS4C1M16F5 数据手册

AS4C1M16F5

Functional description

The AS4C1M16F5 is a high performance 16-megabit CMOS Dynamic Random Access Memory (DRAM) organized as

1,048,576 words × 16 bits. The AS4C1M16F5 is fabricated using advanced CMOS technology and innovative design

techniques resulting in high speed, extremely low power and wide operating margins at component and system levels. The

Alliance 16Mb DRAM family is optimized for use as main memory in personal and portable PCs, workstations, and multimedia

and router switch applications.

The AS4C1M16F5 features high speed page mode operation where read and write operations within a single row (or page)

can be executed at very high speed (15 ns from XCAS)by toggling column addresses within that row. Row and column

addresses are alternately latched into input buffers using the falling edge of RAS and xCAS inputs respectively. Also, RAS is used

to make the column address latch transparent, enabling application of column addresses prior to xCAS assertion. The

AS4C1M16F5 provides dual UCAS and LCAS for independent byte control of read and write access.

Refresh on the 1024 address combinations of A0 to A9 must be performed every 16 ms using:

•

RAS-only refresh: RAS is asserted while xCAS is held high. Each of the 1024 rows must be strobed. Outputs remain high impedence.

• Hidden refresh: xCAS is held low while RAS is toggled. Outputs remain low impedence with previous valid data.

•

CAS-before-RAS refresh (CBR): At least one xCAS is asserted prior to RAS. Refresh address is generated internally.

Outputs are high-impedence (OE and WE are don't care).

• Normal read or write cycles refresh the row being accessed.

The AS4C1M16F5 is available in the standard 42-pin plastic SOJ and the 44/50-pin TSOP II packages, respectively. It operates

with a single power supply of 5V 0.5V. The device provides TTL compatible inputs and outputs.

Logic block diagram

Data

buffers

V_CC

Column decoder

Sense amp

DQ1 to DQ16

GND

RAS clock

generator

RAS

1024 × 1024 × 16

Array

CAS clock

generator

UCAS

LCAS

(16,777,216)

Substrate bias

generator

WE clock

generator

Recommended operating conditions

Parameter

Symbol

V_CC

Min

4.5

0.0

2.4

–0.5^†

Nominal

Max

5.5

0.0

V_CC

0.8

Unit

AS4C1M16F5

5.0

0.0

–

Supply voltage

Input voltage

GND

V_IH

AS4C1M16F5

V_IL

–

Commercial

Industrial

–

Ambient operating temperature

T_A

°C

-40

–

†

min -3.0V for pulse widths less than 5 ns.

Recommended operating conditions apply throughout this document unlesss otherwise specified.

4/11/01; v.0.9.1

Alliance Semiconductor

P. 2 of 21

123 4 5 6 7...21

下载PDF

与AS4C1M16F5相关器件

型号	品牌	描述	获取价格	数据表
AS4C1M16F5-45JC	ALSC	Fast Page DRAM, 1MX16, 45ns, CMOS, PDSO42, 0.400 INCH, PLASTIC, SOJ-42	获取价格
AS4C1M16F5-45TC	ALSC	Fast Page DRAM, 1MX16, 45ns, CMOS, PDSO44, 0.400 INCH, TSOP2-50/44	获取价格
AS4C1M16F5-50JC	ETC	5V 1M X 16 CMOS DRAM	获取价格
AS4C1M16F5-50JI	ETC	5V 1M X 16 CMOS DRAM	获取价格
AS4C1M16F5-50TC	ETC	5V 1M X 16 CMOS DRAM	获取价格
AS4C1M16F5-50TI	ETC	5V 1M X 16 CMOS DRAM	获取价格

产品中心

服务支持

精选活动

关于我们

帮助中心

AS4C1M16F5

AS4C1M16F5 数据手册

与AS4C1M16F5相关器件

与AS4C1M16F5相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

AS4C1M16F5

AS4C1M16F5 数据手册

与AS4C1M16F5相关器件

与AS4C1M16F5相关文章

您还可以找

您在本页遇到什么问题？