Datasheet > 存储 > DRAM> AS4C1M16E5-60TI

AS4C1M16E5-60TI

更新时间： 2024-01-28 08:14:02

品牌	Logo	应用领域
ALSC		动态存储器
页数	文件大小	规格书
22页	601K
描述
5V 1M×16 CMOS DRAM (EDO)

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技术参数
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AS4C1M16E5-60TI 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	SOJ	包装说明：	SOJ, SOJ42,.44
针数：	42	Reach Compliance Code：	unknown
ECCN代码：	EAR99	HTS代码：	8542.32.00.02
风险等级：	5.73	Is Samacsys：	N
访问模式：	FAST PAGE WITH EDO	最长访问时间：	60 ns
其他特性：	RAS ONLY/CAS BEFORE RAS/HIDDEN REFRESH	I/O 类型：	COMMON
JESD-30 代码：	R-PDSO-J42	JESD-609代码：	e0
长度：	27.31 mm	内存密度：	16777216 bit
内存集成电路类型：	EDO DRAM	内存宽度：	16
功能数量：	1	端口数量：	1
端子数量：	42	字数：	1048576 words
字数代码：	1000000	工作模式：	ASYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	1MX16	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	SOJ
封装等效代码：	SOJ42,.44	封装形状：	RECTANGULAR
封装形式：	SMALL OUTLINE	电源：	5 V
认证状态：	Not Qualified	刷新周期：	1024
座面最大高度：	3.76 mm	自我刷新：	YES
最大待机电流：	0.001 A	子类别：	DRAMs
最大压摆率：	0.135 mA	最大供电电压 (Vsup)：	5.5 V
最小供电电压 (Vsup)：	4.5 V	标称供电电压 (Vsup)：	5 V
表面贴装：	YES	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	J BEND	端子节距：	1.27 mm
端子位置：	DUAL	宽度：	10.16 mm
Base Number Matches：	1

AS4C1M16E5-60TI 数据手册

AS4C1M16E5

Functional description

The AS4C1M16E5 is a high performance 16-megabit CMOS Dynamic Random Access Memory (DRAM) organized as 1,048,576 words × 16

bits. The device is fabricated using advanced CMOS technology and innovative design techniques resulting in high speed, extremely low

power and wide operating margins at component and system levels. The Alliance 16Mb DRAM family is optimized for use as main memory

in personal and portable PCs, workstations, and multimedia and router switch applications.

The AS4C1M16E5 features hyper page mode operation where read and write operations within a single row (or page) can be executed at

very high speed by toggling column addresses within that row. Row and column addresses are alternately latched into input buffers using the

falling edge of RAS and xCAS inputs, respectively. Also, RAS is used to make the column address latch transparent, enabling application of

column addresses prior to xCAS assertion. The AS4C1M16E5 provides dual UCAS and LCAS for independent byte control of read and write

access.

Extended data out (EDO), also known as 'hyper-page mode,' enables high speed operation. In contrast to 'fast-page mode' devices, data

remains active on outputs after xCAS is de-asserted high, giving system logic more time to latch the data. Use OE and WE to control output

impedance and prevent bus contention during read-modify-write and shared bus applications. Outputs also go to high impedance at the last

occurrance of RAS and xCAS going high.

Refresh on the 1024 address combinations of A0 to A9 must be performed every 16 ms using:

• RAS-only refresh: RAS is asserted while xCAS is held high. Each of the 1024 rows must be strobed. Outputs remain high impedence.

• Hidden refresh: xCAS is held low while RAS is toggled. Outputs remain low impedence with previous valid data.

• CAS-before-RAS refresh (CBR): At least one xCAS is asserted prior to RAS. Refresh address is generated internally.

Outputs are high-impedence (OE and WE are don't care).

• Normal read or write cycles refresh the row being accessed.

The AS4C1M16E5 is available in the standard 42-pin plastic SOJ and 44/50-pin TSOP II packages, respectively. The AS4C1M16E5 device

operates with a single power supply of 5V 0.5V and provides TTL compatible inputs and outputs.

Logic block diagram

Data

buffers

V_CC

Column decoder

Sense amp

DQ1 to DQ16

GND

RAS clock

generator

RAS

1024 × 1024 × 16

Array

CAS clock

generator

UCAS

LCAS

(16,777,216)

Substrate bias

generator

WE clock

generator

Recommended operating conditions

Parameter

Symbol

V_CC

Min

4.5

0.0

2.4

–0.5^†

Nominal

Max

5.5

0.0

V_CC

0.8

Unit

5.0

0.0

–

Supply voltage

Input voltage

GND

V_IH

V_IL

–

Commercial

Industrial

–

Ambient operating temperature

T_A

°C

-40

–

†

min -3.0V for pulse widths less than 5 ns.

Recommended operating conditions apply throughout this document unless otherwise specified.

4/11/01; v.1.0

Alliance Semiconductor

P. 2 of 22

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与AS4C1M16E5-60TI相关器件

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