AS4C1M16E5
®
Notes
1
2
3
4
5
6
Write cycles may be byte write cycles (either LCAS or UCAS active).
Read cycles may be byte read cycles (either LCAS or UCAS active).
One CAS must be active (either LCAS or UCAS).
I
I
, I , I , and I
are dependent on frequency.
CC6
CC1 CC3 CC4
and I
depend on output loading. Specified values are obtained with the output open.
CC1
CC4
An initial pause of 200 µs is required after power-up followed by any 8 RAS cycles before proper device operation is achieved. In the case of an internal
refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 8 initialization cycles are required after
extended periods of bias without clocks (greater than 8 ms).
7
8
9
AC Characteristics assume t = 2 ns. All AC parameters are measured with a load as described in AC test conditions below.
T
V
(min) and V (max) are reference levels for measuring timing of input signals. Transition times are measured between V and V .
IH
IL
IH
IL
Operation within the t
(max) limit insures that t
(max) can be met. t
(max) is specified as a reference point only. If t
is greater than the
RCD
RAC
RCD
RCD
specified t
(max) limit, then access time is controlled exclusively by t
.
CAC
RCD
10 Operation within the t
(max) limit insures that t
(max) can be met. t (max) is specified as a reference point only. If t
RAD
is greater than the
RAD
RAC
RAD
specified t
(max) limit, then access time is controlled exclusively by t .
AA
RAD
11 Assumes three state test load (5 pF and a 380 Ω Thevenin equivalent).
12 Either t or t must be satisfied for a read cycle.
RCH
RRH
13
t
(max) defines the time at which the output achieves the open circuit condition; it is not referenced to output voltage levels. t
is referenced from
OFF
OFF
rising edge of RAS or CAS, whichever occurs last.
, t , t , t and t are not restrictive operating parameters. They are included in the datasheet as electrical characteristics only.
14
t
WCS WCH RWD CWD
AWD
If tWS ≥ t (min) and tWH ≥ t (min), the cycle is an early write cycle and data out pins will remain open circuit, high impedance, throughout the
WS
WH
cycle. If tRWD ≥ t
(min), t
≥ t
(min) and tAWD ≥ t
(min), the cycle is a read-write cycle and the data out will contain data read from the
RWD
CWD
CWD
AWD
selected cell. If neither of the above conditions is satisfied, the condition of the data out at access time is indeterminate.
15 These parameters are referenced to CAS leading edge in early write cycles and to WE leading edge in read-write cycles.
16 Access time is determined by the longest of t or t or t
CAA
CAC
CPA
17
tASC ≥ t to achieve t (min) and t (max) values.
CP PC CPA
18 These parameters are sampled and not 100% tested.
19 These characteristics apply to AS4C1M16E5 5V devices.
AC test conditions
- Access times are measured with output reference levels of
VOH = 2.4V and VOL = 0.4V,
VIH = 2.4V and VIL = 0.8V
+5V
+3.3V
- Input rise and fall times: 2 ns
Dout
R1 = 828Ω
R1 = 828Ω
Dout
*including scope
and jig capacitance
100 pF*
R2 = 295Ω
50 pF*
R2 = 295Ω
GND
GND
Figure A: Equivalent output load
(AS4C1M16E5)
Figure B: Equivalent output load
(AS4LC1M16E5)
Key to switching waveforms
Rising input
Falling input
Undefined output/don’t care
4/11/01; v.1.0
Alliance Semiconductor
P. 8 of 22
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