Datasheet > AS4C16M16D1A

AS4C16M16D1A

更新时间： 2022-02-26 12:11:07

品牌	Logo	应用领域
ALSC		/
页数	文件大小	规格书
64页	2070K
描述
66-pin TSOPII PACKAGE

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AS4C16M16D1A 数据手册

ꢀ

16Mx16 DDR1-AS4C16M16D1A

Mode Register Set (MRS)

ꢀ

The Mode Register stores the data for controlling various operating modes of a DDR SDRAM. It programs

CAS Latency, Burst Type, and Burst Length to make the DDR SDRAM useful for a variety of applications. The

default value of the Mode Register is not defined; therefore the Mode Register must be written by the user.

Values stored in the register will be retained until the register is reprogrammed. The Mode Register is written by

asserting Low on

, BA1 and BA0 (the device should have all banks idle with no bursts in

CS RAS CAS

progress prior to writing into the mode register, and CKE should be High). The state of address pins A0~A12

and BA0, BA1 in the same cycle in which and are asserted Low is written into the Mode

CS RAS CAS

A0~A2, Burst Type uses A3, and CAS Latency (read latency from column address) uses A4~A6. A logic 0

should be programmed to all the undefined addresses to ensure future compatibility. Reserved states should

not be used to avoid unknown device operation or incompatibility with future versions. Refer to the table for

specific codes for various burst lengths, burst types and CAS latencies.

Table 4. Mode Register Bitmap

BA1 BA0 A12 A11 A10 A9

Address Field

Mode Register

RFU must be set to “0”

T.M.

CAS Latency

Burst Length

A8 A7 Test Mode

A6 A5 A4 CAS Latency A3 Burst Type A2 A1 A0 Burst Length

Reserved

Normal mode

DLL Reset

Test mode

Sequential

Interleave

Reserved

BA0 Mode

Reserved

2.5

Reserved

MRS

EMRS

Reserved

Burst Length Field (A2~A0)

•

This field specifies the data length of column access using the A2~A0 pins and selects the Burst Length to be

2, 4, 8.

Table 5. Burst Length

Burst Length

Reserved

Confidential

- 8/64 -

Rev.1.1

July 2015

1...5 6 789 10 11...64

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