Datasheet > AP0201AT

AP0201AT

更新时间： 2022-06-24 15:40:36

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
31页	473K
描述
AP0201AT High-Dynamic Range (HDR) Image Signal Processor (ISP)

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AP0201AT 数据手册

AP0201AT

SYSTEM INTERFACES

The AP0201AT signals to the sensor and host interfaces

can be at different supply voltage levels to optimize power

consumption and maximize flexibility. Table 3 on page 5

provides the signal descriptions for the AP0201AT.

Figure 3 shows typical AP0201AT device connections.

All power supply rails must be decoupled from ground

using capacitors as close as possible to the package.

PHY

power

Sensor IO

power

1.8 V

(Regulator IP)

1.2 V (Regulator OP)

Power up Core and PLL

OTP

power

HOST IO

power

VDDIO_S

IO_H

CLK

M_S

CLK

DATA

ADDR

RESET_BAR

FRAME_SYNC

EXTCLK_OUT

STANDBY

EXTCLK

RESET_BAR_OUT

XTAL

PHY_RESET_BAR

FV_IN

LV_IN

PIXCLK_IN

DIN[11:0]

MDC

MDIO

TX_CLK

TX_EN

TXD[7:0]

Ethernet MAC Signals

TX_ERR

RX_CLK

CRS_DV

RX_ERR

RXD[7:0]

HISPICN

HISPICP

HISPI0N

HISPI0P

HISPI1N

HISPI1NP

SPI_CS_BAR

GTX_CLK

SPI_S

CLK

SPI_SDO

SPI_SDI

GPIO[6:0]

TRIGGER_OUT

EXT_REG

RESERVED[1:0]

TRST_BAR

GND

IO_S

_REG

(Note 4)

LDO_OP

(Note 4)

IO_OTPM

IO_H

(Note 6)

NOTES: 1. This typical configuration shows only one scenario out of multiple possible variations for this device.

2. ON Semiconductor recommends a 1.5 kW resistor value for the two−wire serial interface R

3. RESET_BAR has an internal pull−up resistor and can be left floating if not used.

PULL−UP

4. The decoupling capacitors for the regulator input and output should have a value of 1.0 mF. The capacitors should be ceramic

and need to have X5R or X7R dielectric.

5. TRST and RESERVED[0] connect to GND for normal operation, RESERVED[3:2] are floating and RESERVED[1] is connected

to VDDIO_H for normal operation.

6. ON Semiconductor recommends that 0.1 mF and 1 mF decoupling capacitors for each power supply are mounted as close as

possible to the pin. Actual values and numbers may vary depending on layout and design consideration.

Figure 3. Typical Ethernet Configuration

www.onsemi.com

1 2 345 6 7...31

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