Datasheet > AN-9033

AN-9033

更新时间： 2022-10-09 17:47:38

品牌	Logo	应用领域
飞兆/仙童 - FAIRCHILD		测试
页数	文件大小	规格书
8页	425K
描述
SPM? TEST BOARD for use in Isolated Inverter GND

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AN-9033 数据手册

External Connection

Signal

Interface 1

(J1)

High-Side Input Signal from CPU (Phase U)

High-Side Input Signal from CPU (Phase V)

High-Side Input Signal from CPU (Phase W)

Low-Side Input Signal from CPU (Phase U)

Low-Side Input Signal from CPU (Phase V)

Low-Side Input Signal from CPU (Phase W)

No connection

Fault-Out Signal to CPU

Bias Supply (+5V) Terminal for Photo coupler Primary Side Driving

Bias Supply GroundTerminal for Photo coupler Primary Side Driving

SPM Bias Supply +15V Terminal for High_Side (Phase W)

SPM Bias Supply Ground Terminal for High_Side (Phase W)

No Connection

Signal

Interface 2

(CN1)

SPM Bias Supply +15V Terminal High_Side (Phase V)

SPM Bias Supply Ground Terminal High_Side (Phase V)

No Connection

SPM Bias Supply +15V Terminal for High_Side (Phase U)

SPM Bias Supply Ground Terminal for High_Side (Phase U)

No Connection

SPM Bias Supply +15V Terminal

SPM Bias Supply Ground Terminal

Positive DC Link Input Connection

Negative DC Link Input Connection

Motor Input Connection (Phase U)

Motor Input Connection (Phase V)

Motor Input Connection (Phase W)

Power

Connection

Rev. A, May 2003

1 2 345 6 7 8

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