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AM27C040-150PE PDF预览

AM27C040-150PE

更新时间: 2024-11-17 22:03:47
品牌 Logo 应用领域
超微 - AMD 可编程只读存储器电动程控只读存储器
页数 文件大小 规格书
13页 168K
描述
4 Megabit (512 K x 8-Bit) CMOS EPROM

AM27C040-150PE 数据手册

 浏览型号AM27C040-150PE的Datasheet PDF文件第2页浏览型号AM27C040-150PE的Datasheet PDF文件第3页浏览型号AM27C040-150PE的Datasheet PDF文件第4页浏览型号AM27C040-150PE的Datasheet PDF文件第5页浏览型号AM27C040-150PE的Datasheet PDF文件第6页浏览型号AM27C040-150PE的Datasheet PDF文件第7页 
FINAL  
Am27C040  
4 Megabit (512 K x 8-Bit) CMOS EPROM  
DISTINCTIVE CHARACTERISTICS  
Fast access time  
Single +5 V power supply  
— Available in speed options as fast as 90 ns  
Low power consumption  
±10% power supply tolerance standard  
100% Flashrite™ programming  
— Typical programming time of 1 minute  
— <10 µA typical CMOS standby current  
Latch-up protected to 100 mA from –1 V to  
JEDEC-approved pinout  
VCC + 1 V  
— Plug-in upgrade for 1 Mbit and 2 Mbit EPROMs  
— Easy upgrade from 28-pin JEDEC EPROMs  
High noise immunity  
Compact 32-pin DIP, PDIP, PLCC packages  
GENERAL DESCRIPTION  
The Am27C040 is a 4 Mbit ultraviolet erasable pro-  
grammable read-only memory. It is organized as 512K  
bytes, operates from a single +5 V supply, has a static  
standby mode, and features fast single address loca-  
tion programming. The device is available in windowed  
ceramic DIP packages and plastic one-time program-  
mable (OTP) packages.  
thus eliminating bus contention in a multiple bus micro-  
processor system.  
AMD’s CMOS process technology provides high  
speed, low power, and high noise immunity. Typical  
power consumption is only 100 mW in active mode,  
and 50 µW in standby mode.  
All signals are TTL levels, including programming sig-  
nals. Bit locations may be programmed singly, in  
blocks, or at random. The device supports AMD’s  
Flashrite programming algorithm (100 µs pulses) re-  
sulting in typical programming time of 1 minute.  
Data can be typically accessed in less than 90 ns, al-  
lowing high-performance microprocessors to operate  
without any WAIT states. The device offers separate  
Output Enable (OE#) and Chip Enable (CE#) controls,  
BLOCK DIAGRAM  
V
Data Outputs  
DQ0–DQ7  
CC  
V
V
SS  
PP  
Output Enable  
Chip Enable  
and  
OE#  
Output  
Buffers  
Prog Logic  
CE#/PGM#  
Y
Y
Gating  
Decoder  
A0–A18  
Address  
Inputs  
X
4,194,304-Bit  
Cell Matrix  
Decoder  
14971G-1  
Publication# 14971 Rev: G Amendment/0  
Issue Date: May 1998  

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