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AM27C040200DC PDF预览

AM27C040200DC

更新时间: 2024-11-18 23:28:47
品牌 Logo 应用领域
其他 - ETC 可编程只读存储器电动程控只读存储器
页数 文件大小 规格书
13页 58K
描述
IC-4MB CMOS EPROM

AM27C040200DC 数据手册

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FINAL  
Am27C040  
4 Megabit (524,288 x 8-Bit) CMOS EPROM  
DISTINCTIVE CHARACTERISTICS  
Fast access time  
±10% power supply tolerance standard on  
most speeds  
— 90 ns  
100% Flashrite™ programming  
— Typical programming time of 1 minute  
Latch-up protected to 100 mA from –1 V to  
Low power consumption  
— 100 µA maximum CMOS standby current  
JEDEC-approved pinout  
V
+ 1 V  
CC  
— Plug in upgrade of 1 Mbit EPROM and 2 Mbit  
EPROMs  
High noise immunity  
Compact 32-pin DIP, PDIP, PLCC,TSOP  
— Easy upgrade from 28-pin JEDEC EPROMs  
packages  
Single +5 V power supply  
GENERAL DESCRIPTION  
The Am27C040 is a 4 Mbit ultraviolet erasable pro-  
grammable read-only memory. It is organized as 512K  
words by 8 bits per word, operates from a single +5 V  
supply, has a static standby mode, and features fast  
single address location programming. Products are  
available in windowed ceramic DIP packages, as well  
as plastic one-time programmable (OTP) packages.  
(CE) controls, thus eliminating bus contention in a mul-  
tiple bus microprocessor system.  
AMD’s CMOS process technology provides high  
speed, low power, and high noise immunity. Typical  
power consumption is only 100 mW in active mode,  
and 100µW in standby mode.  
All signals are TTL levels, including programming sig-  
nals. Bit locations may be programmed singly, in  
blocks, or at random. The Am27C040 supports AMD’s  
Flashrite programming algorithm (100 µs pulses) re-  
sulting in typical programming time of 1 minute.  
Typically, any byte can be accessed in less than 90 ns,  
allowing operation with high-performance micropro-  
cessors without any WAIT states. The Am27C040 of-  
fers separate Output Enable (OE) and Chip Enable  
BLOCK DIAGRAM  
V
Data Outputs  
DQ0–DQ7  
CC  
V
V
SS  
PP  
Output Enable  
Chip Enable  
and  
OE  
Output  
Buffers  
Prog Logic  
CE/PGM  
Y
Y
Gating  
Decoder  
A0–A18  
Address  
Inputs  
X
4,194,304-Bit  
Cell Matrix  
Decoder  
14971E-1  
Publication# 14971 Rev: E Amendment/+1  
Issue Date: July 1997  

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