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ADXL375 PDF预览

ADXL375

更新时间: 2024-09-15 12:52:59
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
32页 534K
描述
3-Axis, 200 g Digital Accelerometer

ADXL375 数据手册

 浏览型号ADXL375的Datasheet PDF文件第2页浏览型号ADXL375的Datasheet PDF文件第3页浏览型号ADXL375的Datasheet PDF文件第4页浏览型号ADXL375的Datasheet PDF文件第5页浏览型号ADXL375的Datasheet PDF文件第6页浏览型号ADXL375的Datasheet PDF文件第7页 
3-Axis, 200 g  
Digital Accelerometer  
ADXL375  
Data Sheet  
FEATURES  
GENERAL DESCRIPTION  
Low power: as low as 35 µA in measurement mode and  
0.1 µA in standby mode at VS = 2.5 V  
Power consumption scales automatically with bandwidth  
Embedded, 32-level FIFO buffer minimizes processor load  
Bandwidth of up to 1 kHz  
The ADXL375 is a small, thin, 3-axis accelerometer that provides  
low power consumption and high resolution measurement up  
to 200 g. The digital output data is formatted as 16-bit, twos  
complement data and is accessible through a SPI (3- or 4-wire)  
or I2C digital interface.  
Bandwidth selectable via serial command  
Shock event detection  
Activity/inactivity monitoring  
Supply voltage range: 2.0 V to 3.6 V  
I/O voltage range: 1.7 V to VS  
SPI (3- or 4-wire) and I2C digital interfaces  
Wide temperature range: −40°C to +85°C  
10,000 g shock survival  
An integrated memory management system with a 32-level first in,  
first out (FIFO) buffer can be used to store data to minimize host  
processor activity and lower overall system power consumption.  
Low power modes enable intelligent motion-based power  
management with threshold sensing and active acceleration  
measurement at extremely low power dissipation.  
The ADXL375 is supplied in a small, thin, 3 mm × 5 mm ×  
1 mm, 14-lead LGA.  
Pb free/RoHS compliant  
Small and thin: 3 mm × 5 mm × 1 mm LGA package  
APPLICATIONS  
Concussion and head trauma detection  
High force event detection  
FUNCTIONAL BLOCK DIAGRAM  
V
V
DD I/O  
S
ADXL375  
POWER  
MANAGEMENT  
INT1  
INT2  
CONTROL  
AND  
INTERRUPT  
LOGIC  
SENSE  
ELECTRONICS  
ADC  
DIGITAL  
FILTER  
3-AXIS  
SENSOR  
SDA/SDI/SDIO  
32-LEVEL  
FIFO  
SERIAL I/O  
SDO/ALT  
ADDRESS  
SCL/SCLK  
GND  
CS  
Figure 1.  
Rev. 0  
Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable. However, no  
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other  
rightsof third parties that may result fromits use. Specifications subject to change without notice. No  
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.  
Trademarks andregisteredtrademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.  
Tel: 781.329.4700  
Technical Support  
©2013 Analog Devices, Inc. All rights reserved.  
www.analog.com  
 
 
 
 

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