Blackfin® Embedded
Symmetric Multiprocessor
ADSP-BF561
Two internal memory-to-memory DMAs and one internal
memory DMA controller
12 general-purpose 32-bit timers/counters with PWM
capability
SPI-compatible port
UART with support for IrDA®
Dual watchdog timers
Dual 32-bit core timers
48 programmable flags (GPIO)
On-chip phase-locked loop capable of 0.5× to 64× frequency
multiplication
Two parallel input/output peripheral interface units support-
ing ITU-R 656 video and glueless interface to analog front
end ADCs
Two dual channel, full duplex synchronous serial ports sup-
porting eight stereo I2S channels
FEATURES
Dual symmetric 600 MHz high performance Blackfin cores
328K bytes of on-chip memory
(see Memory Architecture on Page 4)
Each Blackfin core includes:
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of pro-
gramming and compiler-friendly support
Advanced debug, trace, and performance monitoring
0.8 V to 1.35 V core VDD with on-chip voltage regulator
2.5 V and 3.3 V compliant I/O
256-ball CSP_BGA (two sizes) and 297-ball PBGA
package options
PERIPHERALS
Dual 12-channel DMA controllers
(supporting 24 peripheral DMAs)
Four memory-to-memory DMAs
IRQ CONTROL/
WATCHDOG
TIMER
JTAG TEST
EMULATION
IRQ CONTROL/
WATCHDOG
TIMER
VOLTAGE
REGULATOR
UART
IrDA
B
B
SPI
L1
DATA
MEMORY
L1
DATA
MEMORY
L1
L1
L2 SRAM
128K BYTES
INSTRUCTION
MEMORY
INSTRUCTION
MEMORY
SPORT0
SPORT1
GPIO
IMDMA
CONTROLLER
CORE SYSTEM/BUS INTERFACE
EAB
DMA
CONTROLLER1
32
TIMERS
DMA
CONTROLLER2
DEB
DAB
16
BOOT ROM
16
32
DAB
PAB
EXTERNAL PORT
FLASH/SDRAM CONTROL
PPI0
PPI1
Figure 1. Functional Block Diagram
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Rev. B
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However, no responsibility is assumed by Analog Devices for its use, nor for any
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Specifications subject to change without notice. No license is granted by implication
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