Blackfin® Embedded
Symmetric Multiprocessor
a
ADSP-BF561
FEATURES
PERIPHERALS
Dual symmetric 600 MHz high performance Blackfin cores
328K bytes of on-chip memory (see memory information
on Page 4)
Two parallel input/output peripheral interface units support-
ing ITU-R 656 video and glueless interface to analog front
end ADCs
Two dual channel, full duplex synchronous serial ports sup-
porting eight stereo I2S channels
Dual 16-channel DMA controllers and one internal memory
DMA controller
12 general-purpose 32-bit timers/counters, with PWM
capability
SPI®-compatible port
UART with support for IrDA®
Each Blackfin core includes:
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of program-
ming and compiler-friendly support
Advanced debug, trace, and performance monitoring
0.8 V to 1.35 V core VDD with on-chip voltage regulator
3.3 V and 2.5 V compliant I/O
Dual watchdog timers
256-ball mini-BGA and 297-ball PBGA package options
48 programmable flags
On-chip phase-locked loop capable of 0.5× to 64× frequency
multiplication
IRQ CONTROL/
WATCHDOG
TIMER
JTAG TEST
IRQ CONTROL/
EMULATION
WATCHDOG
TIMER
B B
VOLTAGE
REGULATOR
UART
IrDA
SPI
L1
L1
L1
L1
L2 SRAM
128K BYTES
DATA
MEMORY
DATA
MEMORY
MMU
MMU
INSTRUCTION
MEMORY
INSTRUCTION
MEMORY
SPORT0
SPORT1
GPIO
IMDMA
CONTROLLER
CORE SYSTEM/BUS INTERFACE
EAB
DMA
CONTROLLER1
32
TIMERS
DMA
CONTROLLER2
DEB
DAB
PAB
16
BOOT ROM
32
16
DAB
EXTERNAL PORT
FLASH/SDRAM CONTROL
PPI0
PPI1
Figure 1. Functional Block Diagram
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
Rev. A
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