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ADSP-BF606BBCZ-4 PDF预览

ADSP-BF606BBCZ-4

更新时间: 2024-02-04 15:23:51
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
112页 3197K
描述
Blackfin Dual Core Embedded Processor

ADSP-BF606BBCZ-4 数据手册

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Blackfin Dual Core  
Embedded Processor  
ADSP-BF606/ADSP-BF607/ADSP-BF608/ADSP-BF609  
FEATURES  
MEMORY  
Dual-core symmetric high-performance Blackfin processor,  
up to 500 MHz per core  
Each core contains two 16-bit MACs, two 40-bit ALUs, and a  
40-bit barrel shifter  
RISC-like register and instruction model for ease of  
programming and compiler-friendly support  
Advanced debug, trace, and performance monitoring  
Pipelined Vision Processor provides hardware to process sig-  
nal and image algorithms used for pre- and co-processing  
of video frames in ADAS or other video processing  
applications  
Each core contains 148K bytes of L1 SRAM memory (proces-  
sor core-accessible) with multi-parity bit protection  
Up to 256K bytes of L2 SRAM memory with ECC protection  
Dynamic memory controller provides 16-bit interface to a  
single bank of DDR2 or LPDDR DRAM devices  
Static memory controller with asynchronous memory inter-  
face that supports 8-bit and 16-bit memories  
4 Memory-to-memory DMA streams, 2 of which feature CRC  
protection  
Flexible booting options from flash, SD EMMC and SPI mem-  
ories and from SPI, link port and UART hosts  
Accepts a range of supply voltages for I/O operation. See  
Operating Conditions on Page 52  
Memory management unit provides memory protection  
Off-chip voltage regulator interface  
349-ball BGA package (19 mm × 19 mm), RoHS compliant  
SYSTEM CONTROL BLOCKS  
PERIPHERALS  
2× TWI  
EMULATOR  
TEST & CONTROL  
PLL & POWER  
MANAGEMENT  
FAULT  
MANAGEMENT  
EVENT  
DUAL  
CONTROL  
WATCHDOG  
8× TIMER  
1× COUNTER  
2× PWM  
L2 MEMORY  
CORE 0  
CORE 1  
32K BYTE  
ROM  
3× SPORT  
1× ACM  
B
B
256K BYTE  
148K BYTE  
PARITY BIT PROTECTED  
L1 SRAM  
148K BYTE  
PARITY BIT PROTECTED  
L1 SRAM  
ECC-  
PROTECTED  
SRAM  
INSTRUCTION/DATA  
INSTRUCTION/DATA  
2× UART  
112  
GP  
I/O  
EMMC/RSI  
1× CAN  
DMA SYSTEM  
2× EMAC  
WITH  
2× IEEE 1588  
EXTERNAL  
BUS  
INTERFACES  
2× SPI  
4× LINK PORT  
3× PPI  
PIPELINED  
VISION PROCESSOR  
CRC  
STATIC  
MEMORY  
CONTROLLER  
DYNAMIC  
MEMORY  
CONTROLLER  
VIDEO  
SUBSYSTEM  
HARDWARE  
FUNCTIONS  
PIXEL  
COMPOSITOR  
LPDDR  
DDR2  
16  
USB 2.0 HS OTG  
16  
FLASH  
SRAM  
Figure 1. Processor Block Diagram  
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.  
Rev. 0 Document Feedback  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.  
Tel: 781.329.4700  
Technical Support  
©2013 Analog Devices, Inc. All rights reserved.  
www.analog.com  

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