Blackfin+ Core
Embedded Processor
ADSP-BF700/701/702/703/704/705/706/707
FEATURES
MEMORY
Blackfin+ core with up to 400 MHz performance
Dual 16-bit or single 32-bit MAC support per cycle
16-bit complex MAC and many other instruction set
enhancements
136 kB L1 SRAM with multi-parity-bit protection
(64 kB instruction, 64 kB data, 8 kB scratchpad)
Large on-chip L2 SRAM with ECC protection
256 kB, 512 kB, 1 MB variants
Instruction set compatible with previous Blackfin products
Low-cost packaging
88-Lead LFCSP_VQ (QFN) package (12 mm × 12 mm),
RoHS compliant
On-chip L2 ROM (512 kB)
L3 interface (CSP_BGA only) optimized for lowest system
power, providing 16-bit interface to DDR2 or LPDDR DRAM
devices (up to 200 MHz)
Security and one-time-programmable memory
Crypto hardware accelerators
184-Ball CSP_BGA package (12 mm × 12 mm × 0.8 mm
pitch), RoHS compliant
Low system power with < 100 mW core domain power at
400 MHz (< 0.25 mW/MHz) at 25°C TJUNCTION
Fast secure boot for IP protection
memDMA encryption/decryption for fast run-time security
PERIPHERALS FEATURES
See Figure 1, Processor Block Diagram and Table 1, Processor
Comparison
SYSTEM CONTROL BLOCKS
PERIPHERALS
1× TWI
EMULATOR
TEST & CONTROL
PLL & POWER
MANAGEMENT
FAULT
MANAGEMENT
EVENT
CONTROL
WATCHDOG
8× TIMER
1× COUNTER
2× CAN
L2 MEMORY
UP TO
1M BYTE SRAM
2× UART
512K BYTE
ROM
B
ECC-PROTECTED
(& DMA MEMORY
PROTECTION)
SPI HOST PORT
2x QUAD SPI
136K BYTE PARITY BIT PROTECTED
L1 SRAM INSTRUCTION/DATA
GPIO
1x DUAL SPI
2× SPORT
1× MSI
(SD/SDIO)
SYSTEM FABRIC
1× PPI
EXTERNAL
BUS
INTERFACES
ANALOG
SUB
SYSTEM
HARDWARE
FUNCTIONS
STATIC MEMORY
CONTROLLER
MEMORY
PROTECTION
OTP
MEMORY
SYSTEM PROTECTION
2× CRC
3× MDMA
STREAMS
HADC
CRYPTO ENGINE (SECURITY)
DYNAMIC MEMORY
CONTROLLER
1× RTC
LPDDR
16
1× USB 2.0 HS OTG
DDR2
Figure 1. Processor Block Diagram
Blackfin+ is a trademark of Analog Devices, Inc.; Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.
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