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ADSP-CM402F PDF预览

ADSP-CM402F

更新时间: 2024-01-05 02:53:34
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
84页 2760K
描述
Mixed-Signal Control Processor with ARM Cortex-M4

ADSP-CM402F 数据手册

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Mixed-Signal Control Processor  
with ARM Cortex-M4  
ADSP-CM402F/CM403F/CM407F/CM408F  
Preliminary Technical Data  
Two Serial Peripheral Interface (SPI-compatible) ports  
Eight 32-bit general-purpose timers  
Four Encoder Interfaces, 2 with frequency division  
Single power supply  
176-lead (24 mm × 24 mm) RoHS compliant LQFP package  
120-lead (14 mm × 14 mm) RoHS compliant LQFP package  
SYSTEM FEATURES  
100 MHz to 240 MHz ARM Cortex-M4 with floating-point unit  
128K Byte to 384K Byte zero-wait-state L1 SRAM with  
16K Byte L1 cache  
Up to 2M Byte flash memory  
16-bit asynchronous external memory interface  
Enhanced PWM units  
ANALOG SUBSYSTEM FEATURES  
Four 3rd/4th order SINC filters for glueless connection of iso-  
lated ADCs  
Harmonic analysis engine  
ADC controller (ADCC) and DAC controller (DACC)  
Two 16-bit SAR ADCs with up to 24 multiplexed inputs,  
supporting dual simultaneous conversion in 380 ns (16-bit,  
no missing codes, 3.ꢀLSB INL)  
10/100 Ethernet MAC  
Full Speed USB On-the-Go (OTG)  
Two CAN (controller area network) 2.0B interfaces  
Three UART ports  
Two 12-bit R-string DACs, with output rate up to ꢀ0 kHz  
Two 2.ꢀ V precision voltage reference outputs  
(For details, see ADC/DAC Specifications on Page 36.)  
PERIPHERALS  
SYSTEM CONTROL BLOCKS  
1× TWI  
CoreSight™  
TEST & CONTROL  
PLL & POWER  
MANAGEMENT  
FAULT  
MANAGEMENT  
EVENT  
CONTROL  
SYSTEM  
WATCHDOGS  
4× QUADRATURE  
ENCODER  
12× PWM PAIRS  
8× TIMER  
2× CAN  
L1 CACHE  
L1 MEMORY  
UP TO 384K BYTE  
PARITY-ENABLED  
ZERO-WAIT-STATE SRAM  
16K BYTE  
L1 INSTRUCTION  
CACHE  
3× UART  
Cortex-M4  
2× SPI  
2x SPORT  
SYSTEM FABRIC  
1× EMAC WITH  
IEEE 1588  
(OPTIONAL)  
STATIC MEMORY  
CONTROLLER  
ASYNC INTERFACE  
ANALOG  
SUBSYSTEM  
L3 MEMORY  
HARMONIC ANALYSIS ENGINE  
(HAE)  
UP TO 2M BYTE  
FLASH  
DACC  
ADCC  
SINC FILTERS  
DAC  
ADC  
USB FS OTG  
(OPTIONAL)  
HARDWARE FUNCTIONS  
Figure 1. Block Diagram  
Rev. PrE  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
© 2013 Analog Devices, Inc. All rights reserved.  

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