Mixed-Signal Control Processor
with ARM Cortex-M4
ADSP-CM402F/CM403F/CM407F/CM408F
Preliminary Technical Data
Two Serial Peripheral Interface (SPI-compatible) ports
Eight 32-bit general-purpose timers
Four Encoder Interfaces, 2 with frequency division
Single power supply
176-lead (24 mm × 24 mm) RoHS compliant LQFP package
120-lead (14 mm × 14 mm) RoHS compliant LQFP package
SYSTEM FEATURES
100 MHz to 240 MHz ARM Cortex-M4 with floating-point unit
128K Byte to 384K Byte zero-wait-state L1 SRAM with
16K Byte L1 cache
Up to 2M Byte flash memory
16-bit asynchronous external memory interface
Enhanced PWM units
ANALOG SUBSYSTEM FEATURES
Four 3rd/4th order SINC filters for glueless connection of iso-
lated ADCs
Harmonic analysis engine
ADC controller (ADCC) and DAC controller (DACC)
Two 16-bit SAR ADCs with up to 24 multiplexed inputs,
supporting dual simultaneous conversion in 380 ns (16-bit,
no missing codes, 3.ꢀLSB INL)
10/100 Ethernet MAC
Full Speed USB On-the-Go (OTG)
Two CAN (controller area network) 2.0B interfaces
Three UART ports
Two 12-bit R-string DACs, with output rate up to ꢀ0 kHz
Two 2.ꢀ V precision voltage reference outputs
(For details, see ADC/DAC Specifications on Page 36.)
PERIPHERALS
SYSTEM CONTROL BLOCKS
1× TWI
CoreSight™
TEST & CONTROL
PLL & POWER
MANAGEMENT
FAULT
MANAGEMENT
EVENT
CONTROL
SYSTEM
WATCHDOGS
4× QUADRATURE
ENCODER
12× PWM PAIRS
8× TIMER
2× CAN
L1 CACHE
L1 MEMORY
UP TO 384K BYTE
PARITY-ENABLED
ZERO-WAIT-STATE SRAM
16K BYTE
L1 INSTRUCTION
CACHE
3× UART
Cortex-M4
2× SPI
2x SPORT
SYSTEM FABRIC
1× EMAC WITH
IEEE 1588
(OPTIONAL)
STATIC MEMORY
CONTROLLER
ASYNC INTERFACE
ANALOG
SUBSYSTEM
L3 MEMORY
HARMONIC ANALYSIS ENGINE
(HAE)
UP TO 2M BYTE
FLASH
DACC
ADCC
SINC FILTERS
DAC
ADC
USB FS OTG
(OPTIONAL)
HARDWARE FUNCTIONS
Figure 1. Block Diagram
Rev. PrE
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