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ADSP-BF592 PDF预览

ADSP-BF592

更新时间: 2024-01-15 12:46:40
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
46页 1668K
描述
Blackfin Embedded Processor

ADSP-BF592 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:QFN包装说明:9 X 9 MM, ROHS COMPLIANT, MO-220VMMD-4, LFCSP-64
针数:64Reach Compliance Code:compliant
HTS代码:8542.31.00.01风险等级:5.84
Is Samacsys:N其他特性:ALSO OPERATES AT 2.5 AND 3.3 V TYP
桶式移位器:YES位大小:32
边界扫描:YES最大时钟频率:50 MHz
格式:FIXED POINT内部总线架构:MULTIPLE
JESD-30 代码:S-XQCC-N64长度:9 mm
低功率模式:YES端子数量:64
最高工作温度:70 °C最低工作温度:
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC64,.35SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
电源:1.3,1.8/3.3 V认证状态:Not Qualified
座面最大高度:0.9 mm速度:400 MHz
子类别:Microprocessors最大供电电压:3.6 V
最小供电电压:1.7 V标称供电电压:1.8 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:9 mm
uPs/uCs/外围集成电路类型:DIGITAL SIGNAL PROCESSOR, OTHERBase Number Matches:1

ADSP-BF592 数据手册

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Blackfin  
Embedded Processor  
Preliminary Technical Data  
ADSP-BF592  
FEATURES  
PERIPHERALS  
Up to 400 MHz high-performance Blackfin processor  
2 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,  
40-bit shifter  
RISC-like register and instruction model for ease of  
programming and compiler-friendly support  
Advanced debug, trace, and performance monitoring  
Accepts a wide range of supply voltages for internal and I/O  
operations. See Operating Conditions on Page 18  
Off-chip voltage regulator interface  
4 32-bit timers/counters, three with PWM support  
2 dual-channel, full-duplex synchronous serial ports (SPORT),  
supporting eight stereo I2S channels  
2 Serial Peripheral Interface (SPI) compatible ports  
1 UART with IrDA support  
Parallel peripheral interface (PPI), supporting ITU-R 656  
video data formats  
Two-wire interface (TWI) controller  
9 peripheral DMAs  
64-lead (9 mm × 9 mm) LFCSP package  
2 memory-to-memory DMA channels  
Event handler with 28 interrupt inputs  
32 general-purpose I/Os (GPIOs), with programmable  
hysteresis  
Debug/JTAG interface  
On-chip PLL capable of frequency multiplication  
MEMORY  
68K bytes of core-accessible memory:  
(See Table 1 on Page 3 for L1 and L3 memory size details)  
64K byte L1 instruction ROM  
Flexible booting options from internal L1 ROM and SPI mem-  
ory or from host devices including SPI, PPI, and UART  
Memory management unit providing memory protection  
WATCHDOG TIMER  
SPORT1  
PORT F  
VOLTAGE REGULATOR INTERFACE  
JTAG TEST AND EMULATION  
PERIPHERAL  
PPI  
TIMER2–0  
UART  
SPI0  
ACCESS BUS  
GPIO  
INTERRUPT  
CONTROLLER  
B
L1 INSTRUCTION  
SRAM  
SPORT0  
SPI1  
L1 INSTRUCTION  
ROM  
L1 DATA  
SRAM  
PORT G  
DMA  
CONTROLLER  
DMA  
ACCESS  
BUS  
DCB  
TWI  
DEB  
BOOT  
ROM  
Figure 1. Processor Block Diagram  
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.  
Rev. PrC  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
© 2010 Analog Devices, Inc. All rights reserved.  

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