Blackfin
Embedded Processor
ADSP-BF592
FEATURES
PERIPHERALS
Up to 400 MHz high performance Blackfin processor
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,
40-bit shifter
RISC-like register and instruction model for ease of
programming and compiler-friendly support
Advanced debug, trace, and performance monitoring
Accepts a wide range of supply voltages for internal and I/O
operations, see Operating Conditions on Page 16
Off-chip voltage regulator interface
Four 32-bit timers/counters, three with PWM support
2 dual-channel, full-duplex synchronous serial ports (SPORT),
supporting eight stereo I2S channels
2 serial peripheral interface (SPI) compatible ports
1 UART with IrDA support
Parallel peripheral interface (PPI), supporting ITU-R 656
video data formats
2-wire interface (TWI) controller
9 peripheral DMAs
64-lead (9 mm × 9 mm) LFCSP package
2 memory-to-memory DMA channels
Event handler with 28 interrupt inputs
32 general-purpose I/Os (GPIOs), with programmable
hysteresis
Debug/JTAG interface
On-chip PLL capable of frequency multiplication
MEMORY
68K bytes of core-accessible memory
(See Table 1 on Page 3 for L1 and L3 memory size details)
64K byte L1 instruction ROM
Flexible booting options from internal L1 ROM and SPI mem-
ory or from host devices including SPI, PPI, and UART
Memory management unit providing memory protection
WATCHDOG TIMER
SPORT1
PORT F
VOLTAGE REGULATOR INTERFACE
JTAG TEST AND EMULATION
PERIPHERAL
SPI0
TIMER2–0
UART
PPI
ACCESS BUS
GPIO
INTERRUPT
CONTROLLER
B
L1 INSTRUCTION
SRAM
SPORT0
SPI1
L1 INSTRUCTION
ROM
L1 DATA
SRAM
PORT G
DMA
CONTROLLER
DMA
ACCESS
BUS
DCB
TWI
DEB
BOOT
ROM
Figure 1. Processor Block Diagram
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