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ADSP-BF542BBCZ-5A PDF预览

ADSP-BF542BBCZ-5A

更新时间: 2024-11-29 06:36:27
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
100页 3415K
描述
Embedded Processor

ADSP-BF542BBCZ-5A 数据手册

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Blackfin  
Embedded Processor  
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549  
FEATURES  
PERIPHERALS  
Up to 600 MHz high performance Blackfin processor  
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs  
RISC-like register and instruction model  
Wide range of operating voltages and flexible booting  
options  
High speed USB On-the-Go (OTG) with integrated PHY  
SD/SDIO controller  
ATA/ATAPI-6 controller  
Up to 4 synchronous serial ports (SPORTs)  
Up to 3 serial peripheral interfaces (SPI-compatible)  
Up to 4 UARTs, two with automatic H/W flow control  
Up to 2 CAN (controller area network) 2.0B interfaces  
Up to 2 TWI (2-wire interface) controllers  
8- or 16-bit asynchronous host DMA interface  
Multiple enhanced parallel peripheral interfaces (EPPIs),  
supporting ITU-R BT.656 video formats and 18-/24-bit LCD  
connections  
Media transceiver (MXVR) for connection to a MOST network  
Pixel compositor for overlays, alpha blending, and color  
conversion  
Up to eleven 32-bit timers/counters with PWM support  
Real-time clock (RTC) and watchdog timer  
Up/down counter with support for rotary encoder  
Up to 152 general-purpose I/O (GPIOs)  
Programmable on-chip voltage regulator  
400-ball CSP_BGA, RoHS compliant package  
MEMORY  
Up to 324K bytes of on-chip memory comprised of  
instruction SRAM/cache; dedicated instruction SRAM; data  
SRAM/cache; dedicated data SRAM; scratchpad SRAM  
External sync memory controller supporting either DDR  
SDRAM or mobile DDR SDRAM  
External async memory controller supporting 8-/16-bit async  
memories and burst flash devices  
NAND flash controller  
4 memory-to-memory DMA pairs, 2 with ext. requests  
Memory management unit providing memory protection  
Code security with Lockbox secure technology and 128-bit  
AES/ARC4 data encryption  
On-chip PLL capable of 0.5× to 64× frequency multiplication  
Debug/JTAG interface  
One-time-programmable (OTP) memory  
VOLTAGE  
REGULATOR  
JTAG TEST AND  
EMULATION  
WATCHDOG  
TIMER  
CAN (0-1)  
RTC  
OTP  
TWI (0-1)  
HOST DMA  
UART (0-1)  
UART (2-3)  
SPI (0-1)  
PAB 16  
TIMERS(0-10)  
INTERRUPTS  
B
COUNTER  
KEYPAD  
L2  
SRAM  
L1  
INSTR ROM  
L1  
L1  
DATA SRAM  
INSTR SRAM  
SPI (2)  
32-BIT DMA  
16-BIT DMA  
MXVR  
DAB1 32  
DAB0 16  
DCB 32  
EAB 64  
DEB 32  
SPORT (2-3)  
SPORT (0-1)  
SD / SDIO  
USB  
EXTERNAL PORT  
NOR, DDR, MDDR  
BOOT  
ROM  
ATAPI  
EPPI (0-2)  
DDR/MDDR  
16  
ASYNC  
16  
NAND FLASH  
CONTROLLER  
PIXEL  
COMPOSITOR  
Figure 1. ADSP-BF549 Functional Block Diagram  
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.  
Rev. C  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
© 2010 Analog Devices, Inc. All rights reserved.  

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