Blackfin® Embedded
Symmetric Multi-Processor
a
Preliminary Technical Data
FEATURES
ADSP-BF561
PERIPHERALS
Dual Symmetric 600 Mhz High Performance Blackfin Core
328 KBytes of On-chip Memory (See Memory Info on Page 3)
Each Blackfin Core Includes:
Two 16-Bit MACs, Two 40-Bit ALUs, Four 8-Bit Video ALUs,
40-Bit Shifter
RISC-Like Register and Instruction Model for Ease of Pro-
gramming and Compiler-Friendly Support
Advanced Debug, Trace, and Performance- Monitoring
0.8 - 1.2V core VDD with On-Chip Voltage Regulation
3.3V and 2.5V Tolerant I/O
Two Parallel Input/Output Peripheral Interface Units Sup-
porting ITU-R 656 Video and Glueless Interface to ADI
Analog Front End ADCs
Two Dual Channel, Full Duplex Synchronous Serial Ports Sup-
porting Eight Stereo I2S Channels
Dual 16 Channel DMA Controllers and one internal memory
DMA controller
12 General Purpose 32-bit Timer/Counters, with PWM
Capability
SPI-Compatible Port
UART with Support for IrDA®
Dual Watchdog Timers
256-Ball Mini BGA and 297-Ball PBGA Package Options
48 Programable Flags
On-Chip Phase Locked Loop Capable of 1x to 63x Frequency
Multiplication
IRQ CTRL/
JTAG TEST
IRQ CTRL/
TIMER
TIMER
EMULATION
B B
VOLTAGE
REGULATOR
UART
IRDA®
SPI
L1
L1
DATA
MEMORY
L1
L1
L2 SRAM
DATA
MMU
MMU
INSTRUCTION
MEMORY
INSTRUCTION
MEMORY
128 KBYTES
MEMORY
SPORT0
SPORT1
GPIO
IMDMA
CONTROLLER
CORE SYSTEM / BUS INTERFACE
EAB
DMA
CONTROLLER1
32
TIMERS
DMA
CONTROLLER2
DAB
PAB
16
BOOT ROM
16
32
DAB
EXTERNAL PORT
FLASH/SDRAM CONTROL
PPI
PPI
Figure 1. Functional Block Diagram
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Rev. PrC
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