5秒后页面跳转
ADSP-BF561_06 PDF预览

ADSP-BF561_06

更新时间: 2024-01-01 19:03:12
品牌 Logo 应用领域
亚德诺 - ADI /
页数 文件大小 规格书
60页 2865K
描述
Blackfin Embedded Symmetric Multiprocessor

ADSP-BF561_06 数据手册

 浏览型号ADSP-BF561_06的Datasheet PDF文件第2页浏览型号ADSP-BF561_06的Datasheet PDF文件第3页浏览型号ADSP-BF561_06的Datasheet PDF文件第4页浏览型号ADSP-BF561_06的Datasheet PDF文件第5页浏览型号ADSP-BF561_06的Datasheet PDF文件第6页浏览型号ADSP-BF561_06的Datasheet PDF文件第7页 
Blackfin® Embedded  
Symmetric Multiprocessor  
a
ADSP-BF561  
FEATURES  
PERIPHERALS  
Dual symmetric 600 MHz high performance Blackfin cores  
328K bytes of on-chip memory (see memory information  
on Page 4)  
Two parallel input/output peripheral interface units support-  
ing ITU-R 656 video and glueless interface to analog front  
end ADCs  
Two dual channel, full duplex synchronous serial ports sup-  
porting eight stereo I2S channels  
Dual 16-channel DMA controllers and one internal memory  
DMA controller  
12 general-purpose 32-bit timers/counters, with PWM  
capability  
SPI®-compatible port  
UART with support for IrDA®  
Each Blackfin core includes:  
Two 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs,  
40-bit shifter  
RISC-like register and instruction model for ease of program-  
ming and compiler-friendly support  
Advanced debug, trace, and performance monitoring  
0.8 V to 1.35 V core VDD with on-chip voltage regulator  
3.3 V and 2.5 V compliant I/O  
Dual watchdog timers  
256-ball mini-BGA and 297-ball PBGA package options  
48 programmable flags  
On-chip phase-locked loop capable of 0.5× to 64× frequency  
multiplication  
IRQ CONTROL/  
WATCHDOG  
TIMER  
JTAG TEST  
IRQ CONTROL/  
EMULATION  
WATCHDOG  
TIMER  
B B  
VOLTAGE  
REGULATOR  
UART  
IrDA  
SPI  
L1  
L1  
L1  
L1  
L2 SRAM  
128K BYTES  
DATA  
MEMORY  
DATA  
MEMORY  
MMU  
MMU  
INSTRUCTION  
MEMORY  
INSTRUCTION  
MEMORY  
SPORT0  
SPORT1  
GPIO  
IMDMA  
CONTROLLER  
CORE SYSTEM/BUS INTERFACE  
EAB  
DMA  
CONTROLLER1  
32  
TIMERS  
DMA  
CONTROLLER2  
DEB  
DAB  
PAB  
16  
BOOT ROM  
32  
16  
DAB  
EXTERNAL PORT  
FLASH/SDRAM CONTROL  
PPI0  
PPI1  
Figure 1. Functional Block Diagram  
Blackfin and the Blackfin logo are registered trademarks of Analog Devices, Inc.  
Rev. A  
Information furnished by Analog Devices is believed to be accurate and reliable.  
However, no responsibility is assumed by Analog Devices for its use, nor for any  
infringements of patents or other rights of third parties that may result from its use.  
Specifications subject to change without notice. No license is granted by implication  
or otherwise under any patent or patent rights of Analog Devices. Trademarks and  
registered trademarks are the property of their respective owners.  
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106 U.S.A.  
Tel: 781.329.4700  
Fax: 781.461.3113  
www.analog.com  
© 2006 Analog Devices, Inc. All rights reserved.  

与ADSP-BF561_06相关器件

型号 品牌 获取价格 描述 数据表
ADSP-BF561_07 ADI

获取价格

Blackfin㈢ Embedded Symmetric Multiprocessor
ADSP-BF561SBB500 ADI

获取价格

Blackfin Embedded Symmetric Multi-Processor
ADSP-BF561SBB600 ADI

获取价格

Blackfin Embedded Symmetric Multiprocessor
ADSP-BF561SBBCZ-5A ADI

获取价格

Blackfin Embedded Symmetric Multiprocessor
ADSP-BF561SBBCZ-5A2 ADI

获取价格

Blackfin㈢ Embedded Symmetric Multiprocessor
ADSP-BF561SBBCZ-6A2 ADI

获取价格

Blackfin㈢ Embedded Symmetric Multiprocessor
ADSP-BF561SBBZ500 ADI

获取价格

Blackfin Embedded Symmetric Multiprocessor
ADSP-BF561SBBZ5002 ADI

获取价格

Blackfin㈢ Embedded Symmetric Multiprocessor
ADSP-BF561SBBZ600 ADI

获取价格

Blackfin Embedded Symmetric Multiprocessor
ADSP-BF561SBBZ6002 ADI

获取价格

Blackfin㈢ Embedded Symmetric Multiprocessor