DSP Microcomputer
ADSP-218xN Series
a
PERFORMANCE FEATURES
SYSTEM INTERFACE FEATURES
12.5 ns Instruction cycle time @1.8 V (internal), 80 MIPS sus-
tained performance
Single-cycle instruction execution
Single-cycle context switch
Flexible I/O allows 1.8 V, 2.5 V or 3.3 V operation
All inputs tolerate up to 3.6 V regardless of mode
16-bit internal DMA port for high-speed access to on-chip
memory (mode selectable)
4M-byte memory interface for storage of data tables and pro-
gram overlays (mode selectable)
3-bus architecture allows dual operand fetches in every
instruction cycle
8-bit DMA to byte memory for transparent program and data
memory transfers (mode selectable)
Programmable memory strobe and separate I/O memory
space permits “glueless” system design
Multifunction instructions
Power-down mode featuring low CMOS standby power dissi-
pation with 200 CLKIN cycle recovery from power-down
condition
Programmable wait state generation
Low power dissipation in idle mode
Two double-buffered serial ports with companding hardware
and automatic data buffering
Automatic booting of on-chip program memory from byte-
wide external memory, for example, EPROM, or through
internal DMA Port
INTEGRATION FEATURES
ADSP-2100 family code compatible (easy to use algebraic
syntax), with instruction set extensions
Up to 256K byte of on-chip RAM, configured
Up to 48K words program memory RAM
Up to 56K words data memory RAM
Dual-purpose program memory for both instruction and
data storage
Independent ALU, multiplier/accumulator, and barrel shifter
computational units
Six external interrupts
13 programmable flag pins provide flexible system signaling
UART emulation through software SPORT reconfiguration
ICE-Port™ emulator interface supports debugging in final
systems
Two independent data address generators
Powerful program sequencer provides zero overhead loop-
ing conditional instruction execution
Programmable 16-bit interval timer with prescaler
100-lead LQFP and 144-ball BGA
POWER-DOWN
CONTROL
FULL MEMORY MODE
PROGRAMMABLE
MEMORY
PROGRAM
EXTERNAL
ADDRESS
BUS
DATA
MEMORY
UP TO
DATA ADDRESS
GENERATORS
I/O
MEMORY
UP TO
PROGRAM
SEQUENCER
AND
FLAGS
DAG1
DAG2
EXTERNAL
DATA
BUS
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
BYTE DMA
CONTROLLER
PROGRAM MEMORY DATA
DATA MEMORY DATA
OR
EXTERNAL
DATA
BUS
ARITHMETIC UNITS
SERIAL PORTS
TIMER
INTERNAL
DMA
PORT
ALU
MAC
SHIFTER
SPORT0
SPORT1
ADSP-2100 BASE
ARCHITECTURE
HOST MODE
Figure 1. Functional Block Diagram
ICE-Port is a trademark of Analog Devices, Inc.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106 U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
www.analog.com
© 2006 Analog Devices, Inc. All rights reserved.
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