a
DSP Microcomputer
ADSP-2185
FUNCTIO NAL BLO CK D IAGRAM
FEATURES
PERFORMANCE
30 ns Instruction Cycle Tim e 33 MIPS Sustained
Perform ance
Single-Cycle Instruction Execution
Single-Cycle Context Sw itch
POWER-DOWN
CONTROL
FULL MEMORY
MODE
MEMORY
PROGRAMMABLE
DATA ADDRESS
GENERATORS
I/O
AND
FLAGS
EXTERNAL
ADDRESS
BUS
PROGRAM
MEMORY
DATA
MEMORY
PROGRAM
SEQUENCER
DAG 1 DAG 2
EXTERNAL
DATA
BUS
3-Bus Architecture Allow s Dual Operand Fetches in
Every Instruction Cycle
Multifunction Instructions
Pow er-Dow n Mode Featuring Low CMOS Standby
Pow er Dissipation w ith 100 Cycle Recovery from
Pow er-Dow n Condition
PROGRAM MEMORY ADDRESS
DATA MEMORY ADDRESS
BYTE DMA
CONTROLLER
PROGRAM MEMORY DATA
DATA MEMORY DATA
OR
EXTERNAL
DATA
BUS
ARITHMETIC UNITS
ALU SHIFTER
SERIAL PORTS
SPORT 0 SPORT 1
TIMER
Low Pow er Dissipation in Idle Mode
INTERNAL
DMA
PORT
MAC
INTEGRATION
ADSP-2100 Fam ily Code Com patible, w ith Instruction
Set Extensions
ADSP-2100 BASE
ARCHITECTURE
HOST MODE
80K Bytes of On-Chip RAM, Configured as
16K Words On-Chip Program Mem ory RAM and
16K Words On-Chip Data Mem ory RAM
Dual Purpose Program Mem ory for Both Instruction
and Data Storage
Six External Interrupts
13 Program m able Flag Pins Provide Flexible System
Signaling
UART Em ulation through Softw are SPORT Reconfiguration
ICE-Port™* Em ulator Interface Supports Debugging
in Final System s
Independent ALU, Multiplier/ Accum ulator and Barrel
Shifter Com putational Units
Tw o Independent Data Address Generators
Pow erful Program Sequencer Provides
Zero Overhead Looping Conditional Instruction
Execution
GENERAL NO TE
T his data sheet represents production grade specifications for
the ADSP-2185 (5 V).
Program m able 16-Bit Interval Tim er w ith Prescaler
100-Lead TQFP
GENERAL D ESCRIP TIO N
T he ADSP-2185 is a single-chip microcomputer optimized for
digital signal processing (DSP) and other high speed numeric
processing applications.
SYSTEM INTERFACE
16-Bit Internal DMA Port for High Speed Access to
On-Chip Mem ory (Mode Selectable)
T he ADSP-2185 combines the ADSP-2100 family base archi-
tecture (three computational units, data address generators and
a program sequencer) with two serial ports, a 16-bit internal
DMA port, a byte DMA port, a programmable timer, Flag I/O,
extensive interrupt capabilities and on-chip program and data
memory.
4 MByte Byte Mem ory Interface for Storage of Data
Tables & Program Overlays
8-Bit DMA to Byte Mem ory for Transparent Program
and Data Mem ory Transfers (Mode Selectable)
I/ O Mem ory Interface w ith 2048 Locations Supports
Parallel Peripherals (Mode Selectable)
Program m able Mem ory Strobe & Separate I/ O Mem ory
Space Perm its “Glueless” System Design
(Mode Selectable)
T he ADSP-2185 integrates 80K bytes of on-chip memory con-
figured as 16K words (24-bit) of program RAM and 16K words
(16-bit) of data RAM. Power-down circuitry is also provided to
meet the low power needs of battery operated portable equip-
ment. T he ADSP-2185 is available in 100-pin T QFP package.
Program m able Wait State Generation
Tw o Double-Buffered Serial Ports w ith Com panding
Hardw are and Autom atic Data Buffering
Autom atic Booting of On-Chip Program Mem ory from
Byte-Wide External Mem ory, e.g., EPROM, or
Through Internal DMA Port
In addition, the ADSP-2185 supports new instructions, which
include bit manipulations—bit set, bit clear, bit toggle, bit test—
new ALU constants, new multiplication instruction (x squared),
biased rounding, result free ALU operations, I/O memory trans-
fers and global interrupt masking, for increased flexibility.
*ICE -P or t is a tr adem ar k of Analog D evices, Inc.
REV. 0
Inform ation furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assum ed by Analog Devices for its
use, nor for any infringem ents of patents or other rights of third parties
which m ay result from its use. No license is granted by im plication or
otherwise under any patent or patent rights of Analog Devices.
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© Analog Devices, Inc., 1997