a
DSP Microcomputer
ADSP-218xN Series
PERFORMANCE FEATURES
12.5 ns Instruction Cycle Time @1.8 V (Internal), 80 MIPS
Sustained Performance
Programmable 16-Bit Interval Timer with Prescaler
100-Lead LQFP and 144-Ball Mini-BGA
Single-Cycle Instruction Execution
Single-Cycle Context Switch
3-Bus Architecture Allows Dual Operand Fetches in
Every Instruction Cycle
SYSTEM INTERFACE FEATURES
Flexible I/O Allows 1.8 V, 2.5 V or 3.3 V Operation
All Inputs Tolerate up to 3.6 V Regardless of Mode
16-Bit Internal DMA Port for High-Speed Access to On-
Chip Memory (Mode Selectable)
Multifunction Instructions
Power-Down Mode Featuring Low CMOS Standby
Power Dissipation with 200 CLKIN Cycle Recovery
from Power-Down Condition
4M-Byte Memory Interface for Storage of Data Tables
and Program Overlays (Mode Selectable)
8-Bit DMA to Byte Memory for Transparent Program and
Data Memory Transfers (Mode Selectable)
Programmable Memory Strobe and Separate I/O
Memory Space Permits “Glueless” System Design
Programmable Wait State Generation
Two Double-Buffered Serial Ports with Companding
Hardware and Automatic Data Buffering
Automatic Booting of On-Chip Program Memory from
Byte-Wide External Memory, e.g., EPROM, or through
Internal DMA Port
Low Power Dissipation in Idle Mode
INTEGRATION FEATURES
ADSP-2100 Family Code Compatible (Easy to Use
Algebraic Syntax), with Instruction Set Extensions
Up to 256K Bytes of On-Chip RAM, Configured as
Up to 48K Words Program Memory RAM
Up to 56K Words Data Memory RAM
Dual-Purpose Program Memory for Both Instruction and
Data Storage
Six External Interrupts
Independent ALU, Multiplier/Accumulator, and Barrel
Shifter Computational Units
13 Programmable Flag Pins Provide Flexible System
Signaling
Two Independent Data Address Generators
Powerful Program Sequencer Provides Zero Overhead
Looping Conditional Instruction Execution
UART Emulation through Software SPORT
Reconfiguration
ICE-Port™ Emulator Interface Supports Debugging in
Final Systems
FUNCTIONAL BLOCK DIAGRAM
POWER-DOWN
CONTROL
FULL MEMORY MODE
MEMORY
PROGRAMMABLE
PROGRAM
EXTERNAL
ADDRESS
BUS
DATA
MEMORY
UP TO
DATA ADDRESS
GENERATORS
I/O
MEMORY
AND
FLAGS
PROGRAM
SEQUENCER
UP TO
DAG1 DAG2
48K ꢀ 24-BIT
56K ꢀ 16-BIT
.
e
r
EXTERNAL
DATA
BUS
e
h
m
PROGRAM MEMORY ADDRESS
a
r
g
a
i
d
BYTE DMA
CONTROLLER
k
DATA MEMORY ADDRESS
c
o
l
b
p
i
PROGRAM MEMORY DATA
DATA MEMORY DATA
h
c
OR
t
r
e
s
n
I
EXTERNAL
DATA
BUS
ARITHMETIC UNITS
MAC SHIFTER
SERIAL PORTS
TIMER
INTERNAL
DMA
PORT
ALU
SPORT0
SPORT1
ADSP-2100 BASE
ARCHITECTURE
HOST MODE
ICE-Port is a trademark of Analog Devices, Inc.
REV. 0
Information furnished by Analog Devices is believed to be accurate and reli-
able. However, no responsibility is assumed by Analog Devices for its use,
nor for any infringements of patents or other rights of third parties that may One Technology Way, P.O.Box 9106, Norwood, MA 02062-9106, U.S.A.
result from its use. No license is granted by implication or otherwise under Tel:781/329-4700
any patent or patent rights of Analog Devices. Fax:781/326-8703
http://www.analog.com
© Analog Devices, Inc., 2001